| /third_party/skia/src/core/ |
| D | SkCpu.h | 26 BMI2 = 1 << 11, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
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| D | SkCpu.cpp | 59 if (abcd[1] & (1<<8)) { features |= SkCpu::BMI2; } in read_cpu_features()
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| /third_party/node/deps/v8/src/codegen/ |
| D | cpu-features.h | 26 BMI2, enumerator
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| /third_party/node/deps/v8/src/codegen/x64/ |
| D | assembler-x64.cc | 108 if (cpu.has_bmi2() && FLAG_enable_bmi2) SetSupported(BMI2); in ProbeImpl()
153 CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2), in PrintFeatures()
4028 DCHECK(IsEnabled(BMI2)); in bmi2q()
4037 DCHECK(IsEnabled(BMI2)); in bmi2q()
4046 DCHECK(IsEnabled(BMI2)); in bmi2l()
4055 DCHECK(IsEnabled(BMI2)); in bmi2l()
4063 DCHECK(IsEnabled(BMI2)); in rorxq()
4074 DCHECK(IsEnabled(BMI2)); in rorxq()
4085 DCHECK(IsEnabled(BMI2)); in rorxl()
4096 DCHECK(IsEnabled(BMI2)); in rorxl()
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| /third_party/openssl/doc/man3/ |
| D | OPENSSL_ia32cap.pod | 95 =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
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| /third_party/node/deps/simdutf/ |
| D | simdutf.h | 667 BMI2 = 0x40, enumerator
810 host_isa |= instruction_set::BMI2; in detect_supported_architectures()
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| D | simdutf.cpp | 1267 …_set::AVX2 | internal::instruction_set::BMI1 | internal::instruction_set::BMI2 | internal::instruc… in implementation()
1473 …internal::instruction_set::AVX2 | internal::instruction_set::BMI1 | internal::instruction_set::BMI2 in implementation()
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| /third_party/node/deps/v8/src/codegen/ia32/ |
| D | assembler-ia32.cc | 152 if (cpu.has_bmi2() && FLAG_enable_bmi2) SetSupported(BMI2); in ProbeImpl()
189 CpuFeatures::IsSupported(BMI1), CpuFeatures::IsSupported(BMI2), in PrintFeatures()
3148 DCHECK(IsEnabled(BMI2)); in bmi2()
3156 DCHECK(IsEnabled(BMI2)); in rorx()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleSLM.td | 160 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86ScheduleBdVer2.td | 437 defm : X86WriteResUnsupported<WriteIMulH>; // BMI2 MULX
558 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ScheduleAtom.td | 144 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86Schedule.td | 199 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86ScheduleBtVer2.td | 248 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86SchedSandyBridge.td | 190 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86.td | 220 "Support BMI2 instructions">;
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| D | X86ScheduleZnver2.td | 227 // BMI1 BEXTR, BMI2 BZHI
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| D | X86ScheduleZnver1.td | 239 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86SchedBroadwell.td | 198 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86SchedHaswell.td | 195 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86SchedSkylakeClient.td | 195 // BMI1 BEXTR/BLS, BMI2 BZHI
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| D | X86SchedSkylakeServer.td | 195 // BMI1 BEXTR/BLS, BMI2 BZHI
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| /third_party/node/deps/openssl/openssl/ |
| D | CHANGES.md | 3745 This only affects processors that support the BMI1, BMI2 and ADX extensions
5496 This only affects processors that support the BMI1, BMI2 and ADX extensions
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| /third_party/openssl/ |
| D | CHANGES.md | 3567 This only affects processors that support the BMI1, BMI2 and ADX extensions
5318 This only affects processors that support the BMI1, BMI2 and ADX extensions
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 186 { "bmi2", "Support BMI2 instructions", X86::FeatureBMI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
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