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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp692 uint16_t BX = im(2); in evaluate() local
693 RC[BX] = RC[BX].is(0) ? BT::BitValue::One in evaluate()
694 : RC[BX].is(1) ? BT::BitValue::Zero in evaluate()
701 uint16_t BX = im(2); in evaluate() local
704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero) in evaluate()
705 .fill(W1+(W1-BX), W0, Zero); in evaluate()
706 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1); in evaluate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp100 {codeview::RegisterId::BX, X86::BX}, in initLLVMToSEHAndCVRegMapping()
621 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
633 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
670 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
671 return X86::BX; in getX86SubSuperRegisterOrZero()
706 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
742 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/third_party/ltp/tools/sparse/sparse-src/
Dcompile-i386.c204 AX, DX, CX, BX, SI, DI, BP, SP, // 16-bit enumerator
220 REGINFO( BL, "%bl", BX, EBX, ECX_EBX),
224 REGINFO( BH, "%bh", BX, EBX, ECX_EBX),
228 REGINFO( BX, "%bx", BL, BH, EBX, ECX_EBX),
236 REGINFO(EBX, "%ebx", BL, BH, BX, ECX_EBX),
242 REGINFO(ECX_EBX, "%ecx:%ebx", CL, CH, CX, ECX, BL, BH, BX, EBX),
251 REGSTORAGE(AX), REGSTORAGE(DX), REGSTORAGE(CX), REGSTORAGE(BX),
312 static struct regclass regclass_16 = { "16-bit", { AX, DX, CX, BX, SI, DI, BP }};
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h108 ENTRY(BX) \
122 ENTRY(BX) \
DX86Disassembler.cpp2105 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
2109 baseReg = MCOperand::createReg(X86::BX); in translateRMMemory()
/third_party/node/deps/v8/src/codegen/ppc/
Dassembler-ppc.h460 int BX = 0, TX = 0; in xx2_form() local
463 BX = TX = 1; in xx2_form()
466 emit(instr | (t.code() & 0x1F) * B21 | (b.code() & 0x1F) * B11 | BX * B1 | in xx2_form()
493 int AX = 0, BX = 0, TX = 0; local
496 AX = BX = TX = 1;
500 (b.code() & 0x1F) * B11 | AX * B2 | BX * B1 | TX);
Dassembler-ppc.cc425 case BX: in target_at()
455 *is_branch = (opcode == BX || opcode == BCX); in target_at_put()
459 case BX: { in target_at_put()
542 case BX: in max_reach_from()
723 emit(BX | (imm26 & kImm26Mask) | lk); in b()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.td118 def BX : X86Reg<"bx", 3, [BL,BH]>;
146 def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>;
404 (add AX, CX, DX, SI, DI, BX, BP, SP,
445 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
465 (add AX, CX, DX, SI, DI, BX, BP, SP)>;
/third_party/lz4/programs/
DREADME.md67 -BX : enable block checksum (default:disabled)
Dlz4.1.md188 * `-BX`:
/third_party/lzma/Asm/x86/
D7zAsm.asm108 x3_W equ BX
/third_party/node/deps/v8/src/codegen/arm/
Dconstants-arm.h141 BX = 1 << 4, enumerator
/third_party/pcre2/pcre2/src/sljit/
DsljitNativeARM_T2_32.c119 #define BX 0x4700 macro
1899 return push_inst16(compiler, BX | RN3(TMP_REG2)); in sljit_emit_op_src()
2295 PTR_FAIL_IF(push_inst16(compiler, BX | RN3(TMP_REG1))); in sljit_emit_jump()
2513 PTR_FAIL_IF(push_inst16(compiler, BX | RN3(TMP_REG2))); in sljit_emit_call()
2552 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(src)); in sljit_emit_ijump()
2568 return push_inst16(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RN3(TMP_REG1)); in sljit_emit_ijump()
2611 return push_inst16(compiler, BX | RN3(TMP_REG2)); in sljit_emit_icall()
DsljitNativeARM_32.c97 #define BX 0xe12fff10 macro
2301 return push_inst(compiler, BX | RM(TMP_REG2)); in sljit_emit_op_src()
2721 …PTR_FAIL_IF(push_inst(compiler, (((type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)) & ~COND_MASK) | … in sljit_emit_jump()
2939 PTR_FAIL_IF(push_inst(compiler, BX | RM(TMP_REG2))); in sljit_emit_call()
2977 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(src)); in sljit_emit_ijump()
2982 return push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1)); in sljit_emit_ijump()
2999 FAIL_IF(push_inst(compiler, (type <= SLJIT_JUMP ? BX : BLX) | RM(TMP_REG1))); in sljit_emit_ijump()
3045 return push_inst(compiler, BX | RM(TMP_REG2)); in sljit_emit_icall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
DAArch64SchedKryoDetails.td1510 (instregex "LDRS(BW|BX|HW|HX|W)ui")>;
1516 (instregex "LDRS(BW|BX|HW|HX|W)ro(W|X)")>;
1522 (instregex "LDRS(BW|BX|HW|HX|W)(post|pre)")>;
1540 (instregex "LDTRS(BW|BX|HW|HX|W)i")>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h631 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
DARMAsmPrinter.cpp1321 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in EmitInstruction()
2023 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX) in EmitInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def62 CV_REGISTER(BX, 12)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc196 TmpInst.setOpcode(ARM::BX);
/third_party/rust/crates/memchr/bench/data/sliceslice/
Di386.txt1555 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI.
1557 Figure 2-5 also illustrates that each byte of the 16-bit registers AX, BX,
1649 EBX BH BX BL
1932 of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of
2015 (AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general
9288 MOV BX,FLAT_DES-Temp_GDT
9289 MOV US,BX
9290 MOV ES,BX
9291 MOV SS,BX
9331 MOV BX,GDT_ALIAS ; point DS to GDT alias
[all …]
Di386-notutf8.txt1555 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI.
1557 Figure 2-5 also illustrates that each byte of the 16-bit registers AX, BX,
1649 � EBX BH BX BL �
1932 of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of
2015 (AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general
9288 MOV BX,FLAT_DES-Temp_GDT
9289 MOV US,BX
9290 MOV ES,BX
9291 MOV SS,BX
9331 MOV BX,GDT_ALIAS ; point DS to GDT alias
[all …]
/third_party/pcre2/pcre2/testdata/
Dtestinput10548 /\BX/match_invalid_utf
/third_party/lz4/tests/
DMakefile418 $(LZ4) -BX $(FPREFIX)-hw -c -q | $(LZ4) -tv # test block checksum
/third_party/node/deps/v8/src/diagnostics/ppc/
Ddisasm-ppc.cc1687 case BX: { in InstructionDecode()

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