Home
last modified time | relevance | path

Searched refs:BaseOpcode (Results 1 – 25 of 37) sorted by relevance

12

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp135 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
140 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
141 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
142 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
159 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
50 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4",
55 let PrimaryKey = ["BaseOpcode"];
145 MIMGBaseOpcode BaseOpcode;
154 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
158 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
190 let d16 = !if(BaseOpcode.HasD16, ?, 0);
201 let d16 = !if(BaseOpcode.HasD16, ?, 0);
218 let d16 = !if(BaseOpcode.HasD16, ?, 0);
230 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
[all …]
DAMDGPUInstrInfo.h53 unsigned BaseOpcode; member
DSIISelLowering.cpp5340 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in lowerImage() local
5341 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in lowerImage()
5344 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode); in lowerImage()
5346 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode); in lowerImage()
5347 unsigned IntrOpcode = Intr->BaseOpcode; in lowerImage()
5362 if (BaseOpcode->Atomic) { in lowerImage()
5366 if (BaseOpcode->AtomicX2) { in lowerImage()
5383 unsigned DMaskIdx = BaseOpcode->Store ? 3 : isa<MemSDNode>(Op) ? 2 : 1; in lowerImage()
5386 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in lowerImage()
5388 if (BaseOpcode->Store) { in lowerImage()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
297 let BaseOpcode = "c.f."#NAME;
302 let BaseOpcode = "c.un."#NAME;
307 let BaseOpcode = "c.eq."#NAME;
312 let BaseOpcode = "c.ueq."#NAME;
317 let BaseOpcode = "c.olt."#NAME;
321 let BaseOpcode = "c.ult."#NAME;
325 let BaseOpcode = "c.ole."#NAME;
[all …]
DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
80 string BaseOpcode = instr_asm;
97 string BaseOpcode = instr_asm;
115 string BaseOpcode = instr_asm;
131 string BaseOpcode = instr_asm;
145 string BaseOpcode = instr_asm;
171 string BaseOpcode = instr_asm;
DMipsInstrFPU.td285 let BaseOpcode = "c.f."#NAME;
290 let BaseOpcode = "c.un."#NAME;
295 let BaseOpcode = "c.eq."#NAME;
300 let BaseOpcode = "c.ueq."#NAME;
305 let BaseOpcode = "c.olt."#NAME;
309 let BaseOpcode = "c.ult."#NAME;
313 let BaseOpcode = "c.ole."#NAME;
317 let BaseOpcode = "c.ule."#NAME;
321 let BaseOpcode = "c.sf."#NAME;
326 let BaseOpcode = "c.ngle."#NAME;
[all …]
DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
[all …]
DMicroMips32r6InstrInfo.td614 string BaseOpcode = opstr;
649 string BaseOpcode = instr_asm;
664 string BaseOpcode = opstr;
677 string BaseOpcode = opstr;
688 string BaseOpcode = opstr;
700 string BaseOpcode = opstr;
722 string BaseOpcode = opstr;
735 string BaseOpcode = opstr;
744 string BaseOpcode = opstr;
765 string BaseOpcode = "ldc1";
[all …]
DMipsDSPInstrFormats.td13 // Instructions with the same BaseOpcode and isNVStore values form a row.
14 let RowFields = ["BaseOpcode"];
49 string BaseOpcode = opstr;
DMipsInstrFormats.td42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
119 string BaseOpcode = opstr;
DMips32r6InstrFormats.td17 // Instructions with the same BaseOpcode and isNVStore values form a row.
18 let RowFields = ["BaseOpcode"];
29 string BaseOpcode = opstr;
DMicroMipsInstrInfo.td217 let BaseOpcode = opstr;
228 let BaseOpcode = opstr;
270 string BaseOpcode = opstr;
286 string BaseOpcode = opstr;
592 let BaseOpcode = opstr;
597 let BaseOpcode = opstr;
604 let BaseOpcode = opstr;
611 let BaseOpcode = opstr;
DMicroMipsDSPInstrFormats.td13 string BaseOpcode = opstr;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagon.td128 // Instructions with the same BaseOpcode and isNVStore values form a row.
129 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
144 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
156 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
168 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
180 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
192 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
204 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
286 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
294 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
[all …]
DHexagonDepInstrInfo.td55 let BaseOpcode = "A2_add";
219 let BaseOpcode = "A2_addi";
305 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
356 let BaseOpcode = "A2_asrh";
431 let BaseOpcode = "A2_combinew";
590 let BaseOpcode = "A2_or";
634 let BaseOpcode = "A2_add";
651 let BaseOpcode = "A2_add";
666 let BaseOpcode = "A2_addi";
[all …]
DHexagonPseudo.td168 let BaseOpcode = "call";
200 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
298 isBarrier = 1, BaseOpcode = "JMPret" in {
DHexagonInstrFormats.td170 string BaseOpcode = "";
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1408 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1411 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1425 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1434 emitByte(BaseOpcode + OpcodeOffset, CurByte, OS); in encodeInstruction()
1446 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1453 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1461 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1470 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
1474 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1489 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.h205 MIMGBaseOpcode BaseOpcode; member
220 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
257 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
265 uint16_t BaseOpcode; member
DAMDGPUBaseInfo.cpp113 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
115 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding, in getMIMGOpcode()
122 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
128 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()
135 uint16_t BaseOpcode; member
144 uint16_t BaseOpcode; member
159 return Info ? Info->BaseOpcode : -1; in getMTBUFBaseOpcode()
189 return Info ? Info->BaseOpcode : -1; in getMUBUFBaseOpcode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp494 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst() local
495 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
499 AddrSize = BaseOpcode->NumExtraArgs + in convertMIMGInst()
500 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + in convertMIMGInst()
501 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + in convertMIMGInst()
502 (BaseOpcode->LodOrClampOrMip ? 1 : 0); in convertMIMGInst()
534 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCInstrFormats.td113 string BaseOpcode = "";
408 let BaseOpcode = "ld_rs9";
419 let BaseOpcode = "ld_rs9";
445 let BaseOpcode = "ld_limm";
475 let BaseOpcode = "ld_rlimm";
499 let BaseOpcode = "st_rs9";
510 let BaseOpcode = "st_rs9";
535 let BaseOpcode = "st_limm";
/third_party/node/deps/v8/src/codegen/riscv64/
Dconstants-riscv64.h374 enum BaseOpcode : uint32_t {}; enum
1464 inline int BaseOpcode() const { in BaseOpcode() function
1568 this->BaseOpcode() == OP_FP); in Funct5Value()
1599 this->BaseOpcode() == SYSTEM); in CsrValue()
1606 this->BaseOpcode() == OP_FP); in RoundMode()
1612 this->BaseOpcode() == MISC_MEM)); in MemoryOrder()
1670 DCHECK((this->BaseOpcode() == OP || this->BaseOpcode() == OP_32 || in IsArithShift()
1671 this->BaseOpcode() == OP_IMM || this->BaseOpcode() == OP_IMM_32) && in IsArithShift()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp7608 unsigned BaseOpcode = 0; in expandVecReduce() local
7611 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break; in expandVecReduce()
7612 case ISD::VECREDUCE_FMUL: BaseOpcode = ISD::FMUL; break; in expandVecReduce()
7613 case ISD::VECREDUCE_ADD: BaseOpcode = ISD::ADD; break; in expandVecReduce()
7614 case ISD::VECREDUCE_MUL: BaseOpcode = ISD::MUL; break; in expandVecReduce()
7615 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in expandVecReduce()
7616 case ISD::VECREDUCE_OR: BaseOpcode = ISD::OR; break; in expandVecReduce()
7617 case ISD::VECREDUCE_XOR: BaseOpcode = ISD::XOR; break; in expandVecReduce()
7618 case ISD::VECREDUCE_SMAX: BaseOpcode = ISD::SMAX; break; in expandVecReduce()
7619 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break; in expandVecReduce()
[all …]

12