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Searched refs:CACHELINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/third_party/mesa3d/src/intel/common/
Dintel_clflush.h27 #define CACHELINE_SIZE 64 macro
38 p += CACHELINE_SIZE; in intel_clflush_range()
/third_party/mesa3d/src/intel/vulkan/
Danv_batch_chain.c1918 for (uint32_t l = 0; l < (*bbo)->length; l += CACHELINE_SIZE) in setup_execbuf_for_cmd_buffers()