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Searched refs:CPSR (Results 1 – 25 of 42) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp256 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
304 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
384 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
872 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
900 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
952 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
977 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
992 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
[all …]
DARMInstrThumb.td411 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
415 let Defs = [CPSR];
947 let isCommutable = 1, Uses = [CPSR] in
980 /// instruction modifies the CPSR register.
983 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
984 let hasPostISelHook = 1, Defs = [CPSR] in {
985 let isCommutable = 1, Uses = [CPSR] in
988 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
989 CPSR))]>,
995 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
[all …]
DThumb1InstrInfo.cpp59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
63 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
DARMLowOverheadLoops.cpp698 MIB.addReg(ARM::CPSR); in RevertWhile()
709 (RDA->isRegUsedAfter(MI, ARM::CPSR) || in RevertLoopDec()
710 !RDA->hasSameReachingDef(MI, &MBB->back(), ARM::CPSR))) in RevertLoopDec()
722 MIB.addReg(ARM::CPSR); in RevertLoopDec()
755 MIB.addReg(ARM::CPSR); in RevertLoopEnd()
845 if (!Def->registerDefIsDead(ARM::CPSR, TRI)) { in RemoveLoopUpdate()
DARMBaseInstrInfo.cpp550 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
687 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
923 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
926 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2156 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
2956 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) { in optimizeCompareInstr()
[all …]
DARMFastISel.cpp238 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
250 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
257 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
258 *CPSR = true; in DefinesOptionalPredicate()
295 bool CPSR = false; in AddOptionalDefs() local
296 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
297 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
[all …]
DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1537 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1538 let hasPostISelHook = 1, Defs = [CPSR] in {
1544 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1549 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1556 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1563 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1571 let hasPostISelHook = 1, Defs = [CPSR] in {
1577 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1583 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
[all …]
DARMInstrThumb2.td719 /// changed to modify CPSR.
858 /// instruction modifies the CPSR register.
861 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
862 let hasPostISelHook = 1, Defs = [CPSR] in {
870 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
876 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
885 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
893 let hasPostISelHook = 1, Defs = [CPSR] in {
899 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
[all …]
DARM.td331 /// Some instructions update CPSR partially, which can add false dependency for
333 /// mapped to a separate physical register. Avoid partial CPSR update for these
337 "Avoid CPSR partial update for OOO execution">;
339 /// Disable +1 predication cost for instructions updating CPSR.
344 "Disable +1 predication cost for instructions updating CPSR">;
DThumb2ITBlockPass.cpp173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
DARMExpandPseudoInsts.cpp983 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1006 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1104 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1126 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1391 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
1582 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
DARMAsmPrinter.cpp1680 .addReg(ARM::CPSR) in EmitInstruction()
1736 .addReg(ARM::CPSR) in EmitInstruction()
1867 .addReg(ARM::CPSR) in EmitInstruction()
1886 .addReg(ARM::CPSR) in EmitInstruction()
1901 .addReg(ARM::CPSR) in EmitInstruction()
DARMInstructionSelector.cpp604 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
798 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1156 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
DARMISelLowering.cpp4317 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, in getARMCmp()
4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5081 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5188 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
5237 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
5291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5300 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5317 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
[all …]
DThumb1FrameLowering.cpp417 .addDef(ARM::CPSR) in emitPrologue()
423 .addDef(ARM::CPSR) in emitPrologue()
DREADME-Thumb.txt226 to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
DARMBaseInstrInfo.h481 return MachineOperand::CreateReg(ARM::CPSR,
DARMRegisterInfo.td182 def CPSR : ARMReg<0, "cpsr">;
352 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
DThumb2InstrInfo.cpp496 !MI.definesRegister(ARM::CPSR)) { in rewriteT2FrameIndex()
DARMInstrFormats.td183 // Same as cc_out except it defaults to setting CPSR.
184 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
574 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
1196 // Thumb1 instruction that can either be predicated or set CPSR.
1332 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
/third_party/node/deps/v8/src/codegen/arm/
Dconstants-arm.h224 enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 }; enumerator
243 CPSR_c = CPSR | 1 << 16,
244 CPSR_x = CPSR | 1 << 17,
245 CPSR_s = CPSR | 1 << 18,
246 CPSR_f = CPSR | 1 << 19,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
6886 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
9523 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
9573 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
9580 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
9626 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
9634 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
9832 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10000 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10021 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp901 case Sparc::CPSR: in parseSparcAsmOperand()
1049 RegNo = Sparc::CPSR; in matchRegisterName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp311 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
730 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()

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