| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.h | 177 bool SetFlags, CondARM32::Cond Cond);
180 bool SetFlags, CondARM32::Cond Cond);
183 bool SetFlags, CondARM32::Cond Cond);
186 bool SetFlags, CondARM32::Cond Cond);
188 void b(Label *L, CondARM32::Cond Cond);
193 bool SetFlags, CondARM32::Cond Cond);
199 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL);
201 void clz(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond);
203 void cmn(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
205 void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
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| D | IceAssemblerARM32.cpp | 143 IValueT encodeCondition(CondARM32::Cond Cond) { in encodeCondition() argument
144 return static_cast<IValueT>(Cond); in encodeCondition()
795 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01() argument
807 assert(CondARM32::isDefined(Cond)); in emitType01()
808 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitType01()
815 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
821 emitType01(Cond, Opcode, Rd, Rn, OpSrc1, SetFlags, RuleChecks, InstName); in emitType01()
824 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01() argument
843 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
849 emitType01(Cond, kInstTypeDataRegister, Opcode, SetFlags, Rn, Rd, Src1Value, in emitType01()
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| D | IceTargetLoweringARM32.h | 224 explicit CondWhenTrue(CondARM32::Cond T0,
225 CondARM32::Cond T1 = CondARM32::kNone)
230 CondARM32::Cond WhenTrue0;
231 CondARM32::Cond WhenTrue1;
277 CondARM32::Cond Cond = CondARM32::AL);
315 CondARM32::Cond);
317 CondARM32::Cond);
327 CondARM32::Cond Pred = CondARM32::AL) {
331 CondARM32::Cond Pred = CondARM32::AL) {
339 CondARM32::Cond Pred = CondARM32::AL) {
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| D | IceConverter.cpp | 410 Ice::InstIcmp::ICond Cond; in convertICmpInstruction() local
415 Cond = Ice::InstIcmp::Eq; in convertICmpInstruction()
418 Cond = Ice::InstIcmp::Ne; in convertICmpInstruction()
421 Cond = Ice::InstIcmp::Ugt; in convertICmpInstruction()
424 Cond = Ice::InstIcmp::Uge; in convertICmpInstruction()
427 Cond = Ice::InstIcmp::Ult; in convertICmpInstruction()
430 Cond = Ice::InstIcmp::Ule; in convertICmpInstruction()
433 Cond = Ice::InstIcmp::Sgt; in convertICmpInstruction()
436 Cond = Ice::InstIcmp::Sge; in convertICmpInstruction()
439 Cond = Ice::InstIcmp::Slt; in convertICmpInstruction()
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| D | IceInstARM32.h | 466 static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
515 CondARM32::Cond Predicate) in InstARM32Pred()
518 CondARM32::Cond getPredicate() const { return Predicate; } in getPredicate()
519 void setPredicate(CondARM32::Cond Pred) { Predicate = Pred; } in setPredicate()
521 static const char *predString(CondARM32::Cond Predicate);
539 CondARM32::Cond Predicate;
543 inline StreamType &operator<<(StreamType &Stream, CondARM32::Cond Predicate) {
557 CondARM32::Cond Predicate) { in create()
581 CondARM32::Cond Predicate) in InstARM32UnaryopGPR()
598 CondARM32::Cond Predicate) { in create()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInfo.cpp | 105 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
123 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
124 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
131 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
132 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
145 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
146 Cond.push_back(MI.getOperand(2)); in analyzeBranch()
182 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
185 if (Cond.empty()) { in insertBranch()
193 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
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| D | WebAssemblyLowerBrUnless.cpp | 71 Register Cond = MI->getOperand(1).getReg(); in runOnMachineFunction() local
75 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
76 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
77 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
178 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
193 .addReg(Cond); in runOnMachineFunction()
195 Cond = Tmp; in runOnMachineFunction()
204 .addReg(Cond); in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/crosstest/ |
| D | test_select_main.cpp | 45 TyI1 Cond; in testSelect() local
48 setElement(Cond, j, Index() % 2); in testSelect()
52 Ty ResultLlc = select(Cond, Value1, Value2); in testSelect()
53 Ty ResultSz = Subzero_::select(Cond, Value1, Value2); in testSelect()
60 std::cout << vectAsString<TI1>(Cond) in testSelect()
81 v4si32 Cond; in testSelect() local
84 setElement(Cond, j, Index() % 2); in testSelect()
88 v4f32 ResultLlc = select(Cond, Value1, Value2); in testSelect()
89 v4f32 ResultSz = Subzero_::select(Cond, Value1, Value2); in testSelect()
96 std::cout << vectAsString<v4i1>(Cond) in testSelect()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | LibCallsShrinkWrap.cpp | 95 void shrinkWrapCI(CallInst *CI, Value *Cond);
138 Value *Cond = nullptr; in performCallDomainErrorOnly() local
149 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
160 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
169 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
177 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
183 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
190 Value *Cond = nullptr; in performCallRangeErrorOnly() local
208 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
215 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
133 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
135 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
159 Cond[0].setImm(CC); in reverseBranchCondition()
178 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
213 Cond.clear(); in analyzeBranch()
237 if (Cond.empty()) { in analyzeBranch()
240 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
246 assert(Cond.size() == 1); in analyzeBranch()
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreInstrInfo.cpp | 192 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
274 ArrayRef<MachineOperand> Cond, in insertBranch() argument
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 173 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
351 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
352 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
353 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
373 ArrayRef<MachineOperand> Cond, in insertBranch() argument
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| /third_party/python/Misc/ |
| D | valgrind-python.supp | 39 Memcheck:Cond
153 ### Memcheck:Cond
183 ### Memcheck:Cond
204 Memcheck:Cond
237 Memcheck:Cond
247 Memcheck:Cond
276 Memcheck:Cond
300 Memcheck:Cond
311 ### Memcheck:Cond
322 ### Memcheck:Cond
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 81 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
88 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
91 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
97 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
100 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
107 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
108 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
112 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
113 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
115 MIB.add(Cond[i]); in BuildCondBr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
116 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
134 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
183 ArrayRef<MachineOperand> Cond, in insertBranch() argument
190 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
195 if (Cond.empty()) // Unconditional branch in insertBranch()
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in insertBranch()
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in insertBranch()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 266 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
306 Cond.clear(); in analyzeBranch()
330 if (Cond.empty()) { in analyzeBranch()
371 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
377 assert(Cond.size() == 1); in analyzeBranch()
386 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
401 ArrayRef<MachineOperand> Cond, in insertBranch() argument
408 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
411 if (Cond.empty()) { in insertBranch()
421 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FlagsCopyLowering.cpp | 102 DebugLoc TestLoc, X86::CondCode Cond);
106 X86::CondCode Cond, CondRegArray &CondRegs);
754 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
755 if (Cond != X86::COND_INVALID && !MI.mayStore() && in collectCondsInRegs()
760 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
773 DebugLoc TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
776 TII->get(X86::SETCCr), Reg).addImm(Cond); in promoteCondToReg()
785 DebugLoc TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg() argument
786 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
787 unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)]; in getCondOrInverseInReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 207 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
212 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode())); in parseCondBranch()
213 Cond.push_back(LastInst.getOperand(0)); in parseCondBranch()
214 Cond.push_back(LastInst.getOperand(1)); in parseCondBranch()
239 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
242 Cond.clear(); in analyzeBranch()
288 parseCondBranch(*I, TBB, Cond); in analyzeBranch()
295 parseCondBranch(*std::prev(I), TBB, Cond); in analyzeBranch()
340 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
346 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
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| /third_party/pulseaudio/ |
| D | pulseaudio.supp | 15 Memcheck:Cond
21 Memcheck:Cond
27 Memcheck:Cond
33 Memcheck:Cond
47 Memcheck:Cond
|
| /third_party/skia/tools/ |
| D | valgrind.supp | 26 Memcheck:Cond
86 Memcheck:Cond
165 Memcheck:Cond
173 Memcheck:Cond
269 Memcheck:Cond
275 Memcheck:Cond
281 Memcheck:Cond
290 Memcheck:Cond
306 Memcheck:Cond
|
| /third_party/pcre2/pcre2/testdata/ |
| D | testoutput8-32-3 | 551 9 6 Cond
552 11 1 Cond ref
569 8 1 Cond ref
858 4 6 Cond
859 6 1 Cond ref
862 12 6 Cond
863 14 1 Cond ref
866 20 6 Cond
867 22 1 Cond ref
870 28 6 Cond
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| D | testoutput8-16-3 | 551 12 7 Cond
552 15 1 Cond ref
569 11 1 Cond ref
858 6 8 Cond
859 9 1 Cond ref
862 17 8 Cond
863 20 1 Cond ref
866 28 8 Cond
867 31 1 Cond ref
870 39 8 Cond
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| D | testoutput8-8-3 | 551 17 9 Cond
552 21 1 Cond ref
569 15 1 Cond ref
858 8 11 Cond
859 12 1 Cond ref
862 23 11 Cond
863 27 1 Cond ref
866 38 11 Cond
867 42 1 Cond ref
870 53 11 Cond
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| D | testoutput8-16-4 | 551 12 7 Cond
552 15 1 Cond ref
569 11 1 Cond ref
858 6 8 Cond
859 9 1 Cond ref
862 17 8 Cond
863 20 1 Cond ref
866 28 8 Cond
867 31 1 Cond ref
870 39 8 Cond
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| D | testoutput8-32-2 | 551 9 6 Cond
552 11 1 Cond ref
569 8 1 Cond ref
858 4 6 Cond
859 6 1 Cond ref
862 12 6 Cond
863 14 1 Cond ref
866 20 6 Cond
867 22 1 Cond ref
870 28 6 Cond
[all …]
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