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Searched refs:Disp (Results 1 – 25 of 51) sorted by relevance

123

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr12Encoding() local
188 assert(isUInt<4>(Base) && isUInt<12>(Disp)); in getBDAddr12Encoding()
189 return (Base << 12) | Disp; in getBDAddr12Encoding()
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr20Encoding() local
198 assert(isUInt<4>(Base) && isInt<20>(Disp)); in getBDAddr20Encoding()
199 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); in getBDAddr20Encoding()
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDXAddr12Encoding() local
209 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); in getBDXAddr12Encoding()
210 return (Index << 16) | (Base << 12) | Disp; in getBDXAddr12Encoding()
218 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDXAddr20Encoding() local
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DSystemZInstPrinter.cpp26 void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp, in printAddress() argument
28 O << Disp; in printAddress()
202 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDLAddrOperand() local
204 O << Disp << '(' << Length; in printBDLAddrOperand()
213 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDRAddrOperand() local
215 O << Disp << "(%" << getRegisterName(Length); in printBDRAddrOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DGPRArith.cpp112 #define TestLeaBaseDisp(Base, BaseValue, Disp, Dst) \ in TEST_F() argument
121 Address(Encoded_GPR_##Base(), Disp, AssemblerFixup::NoFixup)); \ in TEST_F()
124 ASSERT_EQ(test.Base##d() + (Disp), test.Dst##d()) \ in TEST_F()
125 << TestString << " with Disp " << Disp; \ in TEST_F()
129 #define TestLeaIndex32bitDisp(Index, IndexValue, Disp, Dst0, Dst1, Dst2, Dst3) \ in TEST_F() argument
138 Address(Encoded_GPR_##Index(), Traits::TIMES_1, Disp, \ in TEST_F()
141 Address(Encoded_GPR_##Index(), Traits::TIMES_2, Disp, \ in TEST_F()
144 Address(Encoded_GPR_##Index(), Traits::TIMES_4, Disp, \ in TEST_F()
147 Address(Encoded_GPR_##Index(), Traits::TIMES_8, Disp, \ in TEST_F()
151 ASSERT_EQ((test.Index##d() << Traits::TIMES_1) + (Disp), test.Dst0##d()) \ in TEST_F()
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DLowLevel.cpp183 #define TestRegAbsoluteAddr(Inst, Dst, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
186 "(" #Inst ", " #Dst ", " #Disp ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
189 __ Inst(IceType_##OpType, Encoded_GPR_##Dst(), Address::Absolute(Disp)); \ in TEST_F()
196 #define TestRegAddrBase(Inst, Dst, Base, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
199 "(" #Inst ", " #Dst ", " #Base ", " #Disp ", " #OpType \ in TEST_F()
203 Address(Encoded_GPR_##Base(), Disp, AssemblerFixup::NoFixup)); \ in TEST_F()
210 #define TestRegAddrScaledIndex(Inst, Dst, Index, Scale, Disp, OpType, \ in TEST_F() argument
214 "(" #Inst ", " #Dst ", " #Index ", " #Scale ", " #Disp ", " #OpType \ in TEST_F()
218 Address(Encoded_GPR_##Index(), Traits::TIMES_##Scale, Disp, \ in TEST_F()
226 #define TestRegAddrBaseScaledIndex(Inst, Dst, Base, Index, Scale, Disp, \ in TEST_F() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp60 int64_t Disp; member
65 : Form(form), DR(dr), Base(), Disp(0), Index(), in SystemZAddressingMode()
91 errs() << " Disp " << Disp; in dump()
159 SDValue &Base, SDValue &Disp) const;
161 SDValue &Base, SDValue &Disp, SDValue &Index) const;
167 SDValue &Base, SDValue &Disp) const;
173 SDValue &Base, SDValue &Disp) const;
180 SDValue &Base, SDValue &Disp, SDValue &Index) const;
192 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) const { in selectBDAddr12Only()
193 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp); in selectBDAddr12Only()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp47 int16_t Disp = 0; member
70 errs() << " Disp " << Disp << '\n'; in dump()
119 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
145 AM.Disp += G->getOffset(); in MatchWrapper()
150 AM.Disp += CP->getOffset(); in MatchWrapper()
187 AM.Disp += Val; in MatchAddress()
230 AM.Disp += Offset; in MatchAddress()
245 SDValue &Base, SDValue &Disp) { in SelectAddr() argument
262 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N), in SelectAddr()
263 MVT::i16, AM.Disp, in SelectAddr()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp85 const MachineOperand *Disp) in MemOpKey() argument
86 : Disp(Disp) { in MemOpKey()
103 return isSimilarDispOp(*Disp, *Other.Disp); in operator ==()
110 const MachineOperand *Disp; member in __anon84ae5aae0111::MemOpKey
136 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key"); in getHashValue()
137 assert(Val.Disp != PtrInfo::getTombstoneKey() && in getHashValue()
147 switch (Val.Disp->getType()) { in getHashValue()
152 Hash = hash_combine(Hash, Val.Disp->getIndex()); in getHashValue()
155 Hash = hash_combine(Hash, Val.Disp->getSymbolName()); in getHashValue()
158 Hash = hash_combine(Hash, Val.Disp->getGlobal()); in getHashValue()
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DX86InstrBuilder.h55 int Disp; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); in getFullAddress()
83 MO.push_back(MachineOperand::CreateImm(Disp)); in getFullAddress()
114 AM.Disp = Op3.getImm(); in getAddressFromInstr()
185 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); in addFullAddress()
187 MIB.addImm(AM.Disp); in addFullAddress()
DX86ISelDAGToDAG.cpp67 int32_t Disp; member
80 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
126 dbgs() << " Disp " << Disp << '\n' in dump()
222 SDValue &Scale, SDValue &Index, SDValue &Disp,
225 SDValue &Scale, SDValue &Index, SDValue &Disp,
229 SDValue &Scale, SDValue &Index, SDValue &Disp,
232 SDValue &Scale, SDValue &Index, SDValue &Disp,
235 SDValue &Scale, SDValue &Index, SDValue &Disp,
239 SDValue &Index, SDValue &Disp,
246 SDValue &Index, SDValue &Disp,
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DX86FixupLEAs.cpp360 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp); in optTwoAddrLEA() local
363 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 || in optTwoAddrLEA()
387 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
410 if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) { in optTwoAddrLEA()
411 bool IsINC = Disp.getImm() == 1; in optTwoAddrLEA()
423 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA()
427 .addReg(BaseReg).addImm(Disp.getImm()) in optTwoAddrLEA()
431 .addReg(BaseReg).addImm(Disp.getImm()); in optTwoAddrLEA()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DGPRArith.cpp124 #define TestLeaBaseDisp(Base, BaseValue, Disp, Dst) \ in TEST_F() argument
134 Address(GPRRegister::Encoded_Reg_##Base, Disp, \ in TEST_F()
138 ASSERT_EQ(test.Base() + (Disp), test.Dst()) \ in TEST_F()
139 << TestString << " with Disp " << Disp; \ in TEST_F()
143 #define TestLeaIndex32bitDisp(Index, IndexValue, Disp, Dst0, Dst1, Dst2, Dst3) \ in TEST_F() argument
151 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_1, Disp, \ in TEST_F()
154 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_2, Disp, \ in TEST_F()
157 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_4, Disp, \ in TEST_F()
160 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_8, Disp, \ in TEST_F()
164 ASSERT_EQ((test.Index() << Traits::TIMES_1) + (Disp), test.Dst0()) \ in TEST_F()
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DLowLevel.cpp137 #define TestRegAbsoluteAddr(Inst, Dst, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
140 "(" #Inst ", " #Dst ", " #Disp ", " #OpType ", " #ByteCountUntyped \ in TEST_F()
144 Address(Disp, AssemblerFixup::NoFixup)); \ in TEST_F()
151 #define TestRegAddrBase(Inst, Dst, Base, Disp, OpType, ByteCountUntyped, ...) \ in TEST_F() argument
154 "(" #Inst ", " #Dst ", " #Base ", " #Disp ", " #OpType \ in TEST_F()
158 Address(GPRRegister::Encoded_Reg_##Base, Disp, \ in TEST_F()
166 #define TestRegAddrScaledIndex(Inst, Dst, Index, Scale, Disp, OpType, \ in TEST_F() argument
170 "(" #Inst ", " #Dst ", " #Index ", " #Scale ", " #Disp ", " #OpType \ in TEST_F()
175 Disp, AssemblerFixup::NoFixup)); \ in TEST_F()
182 #define TestRegAddrBaseScaledIndex(Inst, Dst, Base, Index, Scale, Disp, \ in TEST_F() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp200 uint64_t Disp = Imm & 0xFFFF; in decodeMemRIOperands() local
224 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); in decodeMemRIOperands()
235 uint64_t Disp = Imm & 0x3FFF; in decodeMemRIXOperands() local
245 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); in decodeMemRIXOperands()
256 uint64_t Disp = Imm & 0xFFF; in decodeMemRIX16Operands() local
260 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); in decodeMemRIX16Operands()
271 uint64_t Disp = Imm & 0x1F; in decodeSPE8Operands() local
275 Inst.addOperand(MCOperand::createImm(Disp << 3)); in decodeSPE8Operands()
286 uint64_t Disp = Imm & 0x1F; in decodeSPE4Operands() local
290 Inst.addOperand(MCOperand::createImm(Disp << 2)); in decodeSPE4Operands()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp294 uint64_t Disp = Field & 0xfff; in decodeBDAddr12Operand() local
297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
304 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff); in decodeBDAddr20Operand() local
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
315 uint64_t Disp = Field & 0xfff; in decodeBDXAddr12Operand() local
318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
327 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12); in decodeBDXAddr20Operand() local
330 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDXAddr20Operand()
339 uint64_t Disp = Field & 0xfff; in decodeBDLAddr12Len4Operand() local
342 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDLAddr12Len4Operand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430InstPrinter.cpp71 const MCOperand &Disp = MI->getOperand(OpNo+1); in printSrcMemOperand() local
84 if (Disp.isExpr()) in printSrcMemOperand()
85 Disp.getExpr()->print(O, &MAI); in printSrcMemOperand()
87 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
88 O << Disp.getImm(); in printSrcMemOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp89 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
188 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); in is16BitMemOperand() local
190 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() && in is16BitMemOperand()
191 Disp.getImm() < 0x10000) in is16BitMemOperand()
374 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); in emitMemModRMByte() local
424 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags) in emitMemModRMByte()
428 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, in emitMemModRMByte()
472 if (Disp.isImm() && isDisp8(Disp.getImm())) { in emitMemModRMByte()
473 if (Disp.getImm() == 0 && RMfield != 6) { in emitMemModRMByte()
480 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); in emitMemModRMByte()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRISelDAGToDAG.cpp38 bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
65 SDValue &Disp) { in SelectAddr() argument
73 Disp = CurDAG->getTargetConstant(0, dl, MVT::i8); in SelectAddr()
100 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16); in SelectAddr()
112 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8); in SelectAddr()
225 SDValue Base, Disp; in SelectInlineAsmMemoryOperand() local
227 if (SelectAddr(Op.getNode(), Op, Base, Disp)) { in SelectInlineAsmMemoryOperand()
229 OutOps.push_back(Disp); in SelectInlineAsmMemoryOperand()
263 SDValue Base, Disp; in SelectInlineAsmMemoryOperand() local
282 Disp = CurDAG->getTargetConstant(ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8); in SelectInlineAsmMemoryOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h275 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
282 TargetFlags = Disp.getTargetFlags();
284 switch (Disp.getType()) {
288 return addImm(Disp.getImm() + off);
290 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
293 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
296 return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86Operand.h61 const MCExpr *Disp; member
142 if (Mem.Disp) in print()
143 PrintImmValue(Mem.Disp, ",Disp="); in print()
177 return Mem.Disp; in getMemDisp()
629 CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
634 Res->Mem.Disp = Disp;
649 CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
662 Res->Mem.Disp = Disp;
DX86AsmParser.cpp891 const MCExpr *&Disp,
899 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
1265 const MCExpr *Disp = MCConstantExpr::create(0, getContext()); in DefaultMemSIOperand() local
1266 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp, in DefaultMemSIOperand()
1274 const MCExpr *Disp = MCConstantExpr::create(0, getContext()); in DefaultMemDIOperand() local
1275 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp, in DefaultMemDIOperand()
1409 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm() argument
1423 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size, in CreateMemForInlineAsm()
1441 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End); in CreateMemForInlineAsm()
1447 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg, in CreateMemForInlineAsm()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp119 const MCExpr *Disp; member
185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, in createMem() argument
192 Op->Mem.Disp = Disp; in createMem()
267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); in isMemDisp12()
270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); in isMemDisp20()
307 addExpr(Inst, Mem.Disp); in addBDAddrOperands()
313 addExpr(Inst, Mem.Disp); in addBDXAddrOperands()
320 addExpr(Inst, Mem.Disp); in addBDLAddrOperands()
327 addExpr(Inst, Mem.Disp); in addBDRAddrOperands()
334 addExpr(Inst, Mem.Disp); in addBDVAddrOperands()
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/third_party/typescript/scripts/
DgenerateLocalizedDiagnosticMessages.mjs181 <Disp Icon="Str" />
197 <Disp Icon="Expand" Expand="true" Disp="true" LocTbl="false" />
199 <Disp Icon="Str" Disp="true" LocTbl="false" />${items}
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DFileSystem.h952 CreationDisposition Disp, FileAccess Access,
969 Expected<file_t> openNativeFile(const Twine &Name, CreationDisposition Disp,
1033 CreationDisposition Disp = CD_CreateAlways,
1035 return openFile(Name, ResultFD, Disp, FA_Write, Flags, Mode);
1052 CreationDisposition Disp,
1055 return openNativeFile(Name, Disp, FA_Write, Flags, Mode);
1074 CreationDisposition Disp,
1077 return openFile(Name, ResultFD, Disp, FA_Write | FA_Read, Flags, Mode);
1094 CreationDisposition Disp,
1097 return openNativeFile(Name, Disp, FA_Write | FA_Read, Flags, Mode);
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerX8632.h152 AsmAddress(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup = nullptr) {
153 SetBase(Base, Disp, Fixup);
175 void SetBase(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) { in SetBase() argument
176 if (Fixup == nullptr && Disp == 0 && Base != RegX8632::Encoded_Reg_ebp) { in SetBase()
180 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { in SetBase()
184 SetDisp8(Disp); in SetBase()
189 SetDisp32(Disp); in SetBase()
195 void SetIndex(GPRRegister Index, ScaleFactor Scale, int32_t Disp, in SetIndex() argument
200 SetDisp32(Disp); in SetIndex()
206 int32_t Disp, AssemblerFixup *Fixup) { in SetBaseIndex() argument
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/
Draw_ostream.cpp520 sys::fs::CreationDisposition Disp, sys::fs::FileAccess Access, in getFD() argument
538 EC = sys::fs::openFileForReadWrite(Filename, FD, Disp, Flags); in getFD()
540 EC = sys::fs::openFileForWrite(Filename, FD, Disp, Flags); in getFD()
552 sys::fs::CreationDisposition Disp) in raw_fd_ostream() argument
553 : raw_fd_ostream(Filename, EC, Disp, sys::fs::FA_Write, sys::fs::OF_None) {} in raw_fd_ostream()
566 sys::fs::CreationDisposition Disp, in raw_fd_ostream() argument
569 : raw_fd_ostream(getFD(Filename, EC, Disp, Access, Flags), true) {} in raw_fd_ostream()

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