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Searched refs:DstRC (Results 1 – 25 of 45) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp181 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg) in getCopyRegClasses() local
185 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
189 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
196 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
198 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
199 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy()
261 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
262 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
264 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
[all …]
DAMDGPUInstructionSelector.cpp498 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
500 if (!DstRC) in selectG_MERGE_VALUES()
503 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES()
517 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
556 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
558 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI)) in selectG_UNMERGE_VALUES()
605 const TargetRegisterClass *DstRC = in selectG_INSERT() local
607 if (!DstRC) in selectG_INSERT()
623 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_INSERT()
1272 const TargetRegisterClass *DstRC in selectG_TRUNC() local
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DVOP3Instructions.td146 let Outs64 = (outs DstRC.RegClass:$vdst);
149 let Outs64 = (outs DstRC.RegClass:$vdst);
176 let Outs64 = (outs DstRC.RegClass:$vdst);
196 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
202 let DstRC = RegisterOperand<VGPR_32>;
207 let DstRC = RegisterOperand<VReg_64>;
214 let DstRC = RegisterOperand<VReg_64>;
216 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
DSIInstrInfo.cpp487 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg) in shouldClusterMemOps() local
491 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold; in shouldClusterMemOps()
973 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { in getMovOpcode()
975 if (RI.hasAGPRs(DstRC)) in getMovOpcode()
977 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
978 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
979 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
981 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
2177 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg); in insertSelect() local
2178 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
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DVOP2Instructions.td200 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
241 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
263 let DstRC = RegisterOperand<VGPR_32>;
276 let DstRC = RegisterOperand<VGPR_32>;
351 let Outs32 = (outs DstRC:$vdst);
352 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
365 let Outs32 = (outs DstRC:$vdst);
366 let Outs64 = (outs DstRC:$vdst, VOPDstS64orS32:$sdst);
401 let Outs32 = (outs DstRC:$vdst);
402 let Outs64 = (outs DstRC:$vdst);
DSIInstrInfo.td1742 class getInsDPP <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1753 (ins DstRC:$old, Src0Mod:$src0_modifiers,
1758 (ins DstRC:$old, Src0RC:$src0,
1765 (ins DstRC:$old,
1772 (ins DstRC:$old,
1779 class getInsDPP16 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1782 dag ret = !con(getInsDPP<DstRC, Src0RC, Src1RC, NumSrcArgs,
1787 class getInsDPP8 <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1796 (ins DstRC:$old, Src0Mod:$src0_modifiers,
1800 (ins DstRC:$old, Src0RC:$src0, dpp8:$dpp8, FI:$fi)
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp109 const TargetRegisterClass *DstRC,
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
251 if (SrcRC != DstRC) { in selectCopy()
253 Register ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy()
277 const TargetRegisterClass *DstRC = in selectCopy() local
287 if (DstRC != SrcRC) { in selectCopy()
288 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
297 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { in selectCopy()
298 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
683 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() argument
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DX86InstrMMX.td126 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
129 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
130 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
132 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
133 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
138 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
140 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
141 (ins DstRC:$src1, SrcRC:$src2), asm,
142 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
144 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp154 const TargetRegisterClass *DstRC, in isCrossCopy() argument
159 if (DstRC == SrcRC) in isCrossCopy()
184 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
187 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
189 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
190 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
439 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
488 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
DPeepholeOptimizer.cpp474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
476 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY()
582 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
DRegisterCoalescer.cpp466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
474 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
481 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
485 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
488 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
503 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1325 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local
1327 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1798 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
1803 std::swap(SrcRC, DstRC); in joinCopy()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td657 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
660 dag OutOperandList = (outs DstRC:$rs);
668 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
672 dag OutOperandList = (outs DstRC:$fs);
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
680 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
683 dag OutOperandList = (outs DstRC:$fs);
693 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
696 dag OutOperandList = (outs DstRC:$impl);
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DMipsInstrFPU.td125 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
127 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
132 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
135 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
159 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
161 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
162 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
166 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp100 const TargetRegisterClass *DstRC,
681 const TargetRegisterClass *DstRC; in selectCopy() local
682 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); in selectCopy()
684 if (!DstRC) { in selectCopy()
721 unsigned DstSize = TRI.getRegSizeInBits(*DstRC); in selectCopy()
735 if (!getSubRegForClass(DstRC, TRI, SubReg)) { in selectCopy()
741 selectSubregisterCopy(I, MRI, RBI, SrcReg, SubregRC, DstRC, SubReg); in selectCopy()
774 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
2055 const TargetRegisterClass *DstRC = in select() local
2057 if (!DstRC) in select()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
DPPCVSXSwapRemoval.cpp898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
899 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables()
912 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelect.cpp175 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
176 if (SrcRC == DstRC) { in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
165 DstRC = UseRC; in EmitCopyFromReg()
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
176 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
614 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
616 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.cpp279 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
287 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
DAVRRegisterInfo.h61 const TargetRegisterClass *DstRC,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.h64 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
DHexagonRegisterInfo.cpp242 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
253 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.h90 const TargetRegisterClass *DstRC,
DSystemZRegisterInfo.cpp343 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
351 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.cpp839 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
860 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()

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