| /third_party/vixl/test/aarch32/config/ |
| D | cond-rd-rn-operand-rm-t32.json | 75 "Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
76 // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
233 "Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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| D | cond-rd-rn-operand-const-a32.json | 40 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
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| D | cond-rd-rn-operand-rm-shift-rs-a32.json | 37 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
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| D | cond-rd-rn-operand-const-t32.json | 46 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 39 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 39 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| D | cond-rd-rn-operand-rm-shift-amount-1to31-t32.json | 43 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-shift-amount-1to32-t32.json | 43 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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| D | cond-rd-rn-operand-rm-a32.json | 48 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
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| /third_party/musl/porting/liteos_m_iccarm/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/porting/uniproton/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
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| /third_party/musl/porting/liteos_m/kernel/include/arpa/ |
| D | telnet.h | 20 #define EOR 239 macro
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | constants-arm64.h | 599 EOR = 0x40000000, enumerator
600 EON = EOR | NOT,
614 EOR_w_imm = LogicalImmediateFixed | EOR,
615 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
637 EOR_w = LogicalShiftedFixed | EOR,
638 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedExynosM5.td | 632 def : InstRW<[M5WriteAXW], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Wrs$")>;
633 def : InstRW<[M5WriteAXX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)Xrs$")>;
690 def : InstRW<[M5WriteLGW], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?[BHW]$")>;
691 def : InstRW<[M5WriteLGX], (instregex "^LD(ADD|CLR|EOR|SET|[SU]MAX|[SU]MIN)(A|AL|L)?X$")>;
788 def : InstRW<[M5WriteNALU2], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
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| D | AArch64SchedFalkorDetails.td | 660 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v8i8$")>;
724 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(AND|ORR|ORN|BIC|EOR)v16i8$")>;
898 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^EOR(W|X)r(i|r|s)$")>;
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| D | AArch64SchedExynosM3.td | 496 def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
616 def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
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| D | AArch64SchedExynosM4.td | 594 def : InstRW<[M4WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>;
740 def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | constants-arm.h | 121 EOR = 1 << 21, // Logical Exclusive OR. enumerator
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| /third_party/vixl/src/aarch64/ |
| D | constants-aarch64.h | 743 EOR = 0x40000000, enumerator
744 EON = EOR | NOT,
758 EOR_w_imm = LogicalImmediateFixed | EOR,
759 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
781 EOR_w = LogicalShiftedFixed | EOR,
782 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
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| D | macro-assembler-aarch64.cc | 859 LogicalMacro(rd, rn, operand, EOR); in Emit()
916 case EOR: in Emit()
935 case EOR: in Emit()
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| /third_party/python/Lib/ |
| D | telnetlib.py | 97 EOR = bytes([25]) # end or record variable
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_32.c | 102 #define EOR 0xe0200000 macro
1501 return push_inst(compiler, (EOR ^ 0xf0000000) | SRC2_IMM | RD(dst) | RN(dst) | 0x1f); in emit_single_op()
1557 …return push_inst(compiler, EOR | (flags & SET_FLAGS) | RD(dst) | RN(src1) | ((src2 & SRC2_IMM) ? s… in emit_single_op()
2281 FAIL_IF(push_inst(compiler, EOR | SRC2_IMM | RD(TMP_REG2) | RN(src2) | 0x1f)); in sljit_emit_shift_into()
3117 ins = (op == SLJIT_AND ? AND : (op == SLJIT_OR ? ORR : EOR)); in sljit_emit_op_flags()
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| D | sljitNativeARM_64.c | 87 #define EOR 0xca000000 macro
857 FAIL_IF(push_inst(compiler, (EOR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2))); in emit_op_imm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRExpandPseudoInsts.cpp | 1524 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr) in expand() local
1530 EOR->getOperand(3).setIsDead(); in expand()
|