| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 281 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
282 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
317 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
318 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
326 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); in extendRegister() local
327 MIRBuilder.buildSExt(ExtReg, ValReg); in extendRegister()
328 return ExtReg; in extendRegister()
331 Register ExtReg = MRI.createGenericVirtualRegister(LocTy); in extendRegister() local
332 MIRBuilder.buildZExt(ExtReg, ValReg); in extendRegister()
333 return ExtReg; in extendRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 128 Register ExtReg; in assignValueToReg() local
142 ExtReg = MIB->getOperand(0).getReg(); in assignValueToReg()
144 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
151 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
155 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 123 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
133 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
137 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 54 Register ExtReg; in assignValueToReg() local
58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in assignValueToReg()
60 ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
62 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| D | AMDGPUInstructionSelector.cpp | 1383 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
1386 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
1393 .addReg(ExtReg) in selectG_SZA_EXT()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 259 Register narrowExtendRegIfNeeded(Register ExtReg,
4539 Register ExtReg = in selectAddrModeWRO() local
4545 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
4771 Register ExtReg, MachineIRBuilder &MIB) const { in narrowExtendRegIfNeeded() argument
4773 if (MRI.getType(ExtReg).getSizeInBits() == 32) in narrowExtendRegIfNeeded()
4774 return ExtReg; in narrowExtendRegIfNeeded()
4778 auto Copy = MIB.buildCopy({NarrowReg}, {ExtReg}); in narrowExtendRegIfNeeded()
4796 Register ExtReg; in selectArithExtendedRegister() local
4823 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
4829 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
[all …]
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| D | AArch64CallLowering.cpp | 172 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
173 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 934 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
935 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
937 SrcReg1 = ExtReg; in PPCEmitCmp()
940 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
943 SrcReg2 = ExtReg; in PPCEmitCmp()
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| D | PPCISelLowering.cpp | 10708 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
10710 ExtReg).addReg(dest); in EmitAtomicBinary()
10712 .addReg(incr).addReg(ExtReg); in EmitAtomicBinary()
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