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Searched refs:FMAD (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h360 FMAD, enumerator
DTargetLowering.h2533 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegalForFAddFSub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp517 case ISD::FMAD: in fnegFoldsIntoOp()
1593 (unsigned)ISD::FMAD; in LowerDIVREM24()
1676 unsigned FMAD = MFI->getMode().FP32Denormals ? in LowerUDIVREM64() local
1678 (unsigned)ISD::FMAD; in LowerUDIVREM64()
1682 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1691 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
3735 case ISD::FMAD: { in performFNegCombine()
DSIISelLowering.cpp382 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
523 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
782 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
8598 case ISD::FMAD: in fp16SrcZerosHighBits()
8767 case ISD::FMAD: in isCanonicalized()
9444 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
9445 return ISD::FMAD; in getFusedOpcode()
DR600ISelLowering.cpp231 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
DAMDGPUISelDAGToDAG.cpp904 case ISD::FMAD: in Select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp258 case ISD::FMAD: return "fmad"; in getOperationName()
DLegalizeFloatTypes.cpp2138 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
DTargetLowering.cpp5568 case ISD::FMAD: { in isNegatibleForFree()
5678 case ISD::FMAD: { in getNegatedExpression()
DDAGCombiner.cpp11546 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
11764 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
12058 (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFMULForFMADistributiveCombine()
12065 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMADistributiveCombine()
DLegalizeDAG.cpp3208 case ISD::FMAD: in ExpandNode()
DSelectionDAG.cpp4139 case ISD::FMAD: { in isKnownNeverNaN()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp645 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td439 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
/third_party/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md7688 ### FMAD ### subsection
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp37228 case ISD::FMAD: in scalarizeExtEltFP()