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Searched refs:FP1 (Results 1 – 13 of 13) sorted by relevance

/third_party/libcoap/src/
Dcoap_net.c892 #define FP1 Q(FRAC_BITS, ((coap_fixed_point_t){1,0})) in coap_calc_timeout() macro
899 result = SHR_FP((ACK_RANDOM_FACTOR - FP1) * r, MAX_BITS); in coap_calc_timeout()
903 result = SHR_FP(((result + FP1) * ACK_TIMEOUT), FRAC_BITS); in coap_calc_timeout()
909 #undef FP1 in coap_calc_timeout()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td33 list<Register> FP_RET = [FP0, FP1];
257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>>
269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
DX86RegisterInfo.td203 def FP1 : X86Reg<"fp1", 0>;
DX86FastISel.cpp1218 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
3567 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && in fastLowerCall()
DX86InstrCompiler.td474 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
494 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
DX86ISelLowering.cpp2713 VA.getLocReg() == X86::FP1) { in LowerReturn()
3023 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts. in LowerCallResult()
3031 VA.convertToReg(X86::FP1); // Set reg to FP1, avoid hitting asserts. in LowerCallResult()
3039 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
4551 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in IsEligibleForTailCallOptimization()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc2841 X86::FP0, X86::FP1
2912 X86::FP0, X86::FP1
3122 X86::FP0, X86::FP1
3698 X86::FP0, X86::FP1
3912 X86::FP0, X86::FP1
DX86GenRegisterInfo.inc124 FP1 = 104,
1224 { X86::FP1 },
1706 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
1946 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2406 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
DX86GenInstrInfo.inc16673 static const MCPhysReg ImplicitList104[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86:…
16674 …, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3…
DX86GenAsmMatcher.inc7197 case X86::FP1: OpKind = MCK_RFP32; break;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp117 {codeview::RegisterId::ST1, X86::FP1}, in initLLVMToSEHAndCVRegMapping()
/third_party/skia/third_party/externals/opengl-registry/extensions/NV/
DNV_fragment_program.txt381 RESOLVED: Yes, "!!FP1.0", identifying the first revision of this
1373 <progPrefix> ::= "!!FP1.0"
4011 instructions in any !!FP1.0 program is 1024. If ARB_fragment_program is
4012 supported, the maximum number of executable instructions for an !!FP1.0 is
4263 70 03/20/03 pbrown Made the instruction count limit for !!FP1.0
/third_party/openGLES/extensions/NV/
DNV_fragment_program.txt381 RESOLVED: Yes, "!!FP1.0", identifying the first revision of this
1373 <progPrefix> ::= "!!FP1.0"
4011 instructions in any !!FP1.0 program is 1024. If ARB_fragment_program is
4012 supported, the maximum number of executable instructions for an !!FP1.0 is
4263 70 03/20/03 pbrown Made the instruction count limit for !!FP1.0