| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 83 def : WriteRes<FPU, [Z196_FPUnit]>;
88 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
718 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
719 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
744 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
748 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
749 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
754 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
756 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
757 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
|
| D | SystemZScheduleZEC12.td | 84 def : WriteRes<FPU, [ZEC12_FPUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
756 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
757 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
782 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
786 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
787 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
792 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
794 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
795 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
[all …]
|
| D | SystemZSchedule.td | 52 def "FPU"#Num : SchedWrite;
|
| /third_party/elfutils/tests/ |
| D | run-addrcfi.sh | 68 FPU-control reg37 (%fctrl): undefined
69 FPU-control reg38 (%fstat): undefined
70 FPU-control reg39 (%mxcsr): undefined
115 FPU-control reg37 (%fctrl): undefined
116 FPU-control reg38 (%fstat): undefined
117 FPU-control reg39 (%mxcsr): undefined
334 FPU reg32 (f0): undefined
335 FPU reg33 (f1): undefined
336 FPU reg34 (f2): undefined
337 FPU reg35 (f3): undefined
[all …]
|
| D | run-allregs.sh | 43 FPU-control registers:
191 FPU registers:
1214 FPU registers:
2219 FPU registers:
2292 FPU registers:
2381 FPU registers:
2459 FPU registers:
2553 FPU registers:
2826 FPU registers:
2873 FPU registers:
|
| /third_party/node/deps/v8/src/codegen/ |
| D | cpu-features.h | 48 FPU,
56 FPU,
66 FPU,
76 FPU,
|
| /third_party/musl/ |
| D | INSTALL | 60 * Default ABI variant uses FPU registers; alternate soft-float ABI
61 that does not use FPU registers or instructions is available
69 * Default ABI variant uses FPU registers; alternate soft-float ABI
70 that does not use FPU registers or instructions is available
90 * Full FPU ABI or soft-float ABI is supported, but the
91 single-precision-only FPU ABI is not
|
| /third_party/rust/crates/minimal-lexical/ |
| D | CHANGELOG | 19 …eature, which adds inline ASM to use FPU instructions for to ensure proper rounding on x86 targets…
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMELFStreamer.cpp | 98 void emitFPU(unsigned FPU) override;
233 void ARMTargetAsmStreamer::emitFPU(unsigned FPU) { in emitFPU() argument
234 OS << "\t.fpu\t" << ARM::getFPUName(FPU) << "\n"; in emitFPU()
305 unsigned FPU = ARM::FK_INVALID; member in __anon65e2e86b0111::ARMTargetELFStreamer
409 void emitFPU(unsigned FPU) override;
903 FPU = Value; in emitFPU()
907 switch (FPU) { in emitFPUDefaultAttributes()
1033 report_fatal_error("Unknown FPU: " + Twine(FPU)); in emitFPUDefaultAttributes()
1072 if (FPU != ARM::FK_INVALID) in finishAttributeSection()
1135 FPU = ARM::FK_INVALID; in finishAttributeSection()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
| D | ARMTargetParser.cpp | 252 unsigned ARM::parseFPU(StringRef FPU) { in parseFPU() argument
253 StringRef Syn = getFPUSynonym(FPU); in parseFPU()
324 StringRef ARM::getFPUSynonym(StringRef FPU) { in getFPUSynonym() argument
325 return StringSwitch<StringRef>(FPU) in getFPUSynonym()
338 .Default(FPU); in getFPUSynonym()
|
| /third_party/ffmpeg/libavutil/arm/ |
| D | asm.S | 44 # define FPU macro
46 # define FPU @ macro
71 FPU .fpu neon label
75 FPU .fpu vfp label
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 49 // Mips 32-bit FPU Registers
52 // Mips 64-bit (aliased) FPU Registers
154 /// Mips Single point precision FPU Registers
162 /// Mips Double point precision FPU Registers (aliased
169 /// Mips Double point precision FPU Registers in MFP64 mode.
175 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
428 // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP8.td | 27 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
41 // The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
44 // FPU, so keep in mind that FPU==VSU.
394 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
|
| D | PPCScheduleE500mc.td | 25 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
36 def E500mc_FPU_0 : FuncUnit; // FPU pipeline
|
| D | PPCScheduleE5500.td | 26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
39 def E5500_FPU_0 : FuncUnit; // FPU pipeline
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | ARMTargetParser.h | 247 StringRef getFPUSynonym(StringRef FPU);
252 unsigned parseFPU(StringRef FPU);
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleBdVer2.td | 61 // Four FPU pipes.
63 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0
64 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1
65 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2
66 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3
68 // FPU grouping
108 // FPU Pipeline Scheduling
111 // The FPU unit is shared between the two cores.
|
| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | assembler-loong64-inl.h | 16 bool CpuFeatures::SupportsOptimizer() { return IsSupported(FPU); } in SupportsOptimizer()
|
| /third_party/python/Modules/_decimal/libmpdec/ |
| D | README.txt | 77 mulmod-ppro.txt -> Proof for the x87 FPU modular multiplication
|
| /third_party/ffmpeg/tests/checkasm/arm/ |
| D | checkasm.S | 27 FPU .fpu vfp label
|
| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | assembler-mips64-inl.h | 48 bool CpuFeatures::SupportsOptimizer() { return IsSupported(FPU); } in SupportsOptimizer()
|
| /third_party/node/deps/v8/src/codegen/s390/ |
| D | assembler-s390.cc | 252 supported_ |= (1u << FPU); in ProbeImpl()
274 PrintF("FPU=%d\n", CpuFeatures::IsSupported(FPU)); in PrintFeatures()
|
| /third_party/alsa-lib/ |
| D | INSTALL | 99 Configuration for machines without FPU
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| D | assembler-mips-inl.h | 48 bool CpuFeatures::SupportsOptimizer() { return IsSupported(FPU); } in SupportsOptimizer()
|
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | assembler-riscv64-inl.h | 46 bool CpuFeatures::SupportsOptimizer() { return IsSupported(FPU); } in SupportsOptimizer()
|