| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Utils/ |
| D | ARMBaseInfo.h | 41 GE, // Greater than or equal Greater than or equal enumerator
61 case GE: return LT; in getOppositeCondition()
62 case LT: return GE; in getOppositeCondition()
80 case ARMCC::GE: return ARMCC::LE; in getSwappedCondition()
83 case ARMCC::LE: return ARMCC::GE; in getSwappedCondition()
158 case ARMCC::GE: return "ge"; in ARMCondCodeToString()
181 .Case("ge", ARMCC::GE) in ARMCondCodeFromString()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.def | 39 X(Oge , GE , kNone, ge , none , false, false) \
63 X(Sgt, true , true , GT, LT , GE , gt , false, false) \
64 X(Sge, true , false , GE, GE , LT , ge , false, false) \
65 X(Slt, true , false , LT, LT , GE , gt , true , false) \
66 X(Sle, true , true , LE, GE , LT , ge , true , false)
|
| D | IceInstARM32.def | 118 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
119 X(LT, 11, GE, "lt") /* signed less than */ \
|
| /third_party/ltp/testcases/lib/ |
| D | tst_kvcmp.c | 15 GE, enumerator
33 return GE; in strtop()
129 case GE: in main()
172 case GE: in main()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTX.h | 33 GE enumerator
137 GE, enumerator
|
| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_compiler_nir_emit.c | 73 …OPC(seq, SET, 0_1_X, EQ), OPC(sne, SET, 0_1_X, NE), OPC(sge, SET, 0_1_X, GE), OPC(slt, SET, 0_1_X,…
106 OPC(fge32, CMP, 0_1_X, GE),
110 IOPC(ige32, CMP, 0_1_X, GE),
112 UOPC(uge32, CMP, 0_1_X, GE),
|
| /third_party/mesa3d/src/amd/common/ |
| D | ac_perfcounter.h | 92 GE = 0x21, enumerator
93 GE1 = GE,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | MetaRenamer.cpp | 105 for (auto GI = M.global_begin(), GE = M.global_end(); GI != GE; ++GI) { in runOnModule() local
|
| /third_party/node/deps/v8/src/base/ |
| D | logging.h | 334 DEFINE_SIGNED_MISMATCH_COMP(is_signed_vs_unsigned, GE, !CmpLTImpl(lhs, rhs))
340 DEFINE_SIGNED_MISMATCH_COMP(is_unsigned_vs_signed, GE, CmpLEImpl(rhs, lhs))
373 DEFINE_CHECK_OP_IMPL(GE, >=)
381 #define CHECK_GE(lhs, rhs) CHECK_OP(GE, >=, lhs, rhs)
398 #define DCHECK_GE(lhs, rhs) DCHECK_OP(GE, >=, lhs, rhs)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 87 // Parallel selection, reads the GE flags.
96 // Writes to the GE bits.
103 // Writes to the GE bits.
106 // Writes to the GE bits.
117 // Writes to the GE bits.
137 // Writes to the GE bits.
140 // Writes to the GE bits.
151 // Writes to the GE bits.
154 // Writes to the GE bits.
157 // Writes to the GE bits.
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/MCTargetDesc/ |
| D | ARCInfo.h | 35 GE = 0xa, enumerator
|
| /third_party/icu/icu4c/source/data/region/ |
| D | os.txt | 17 GE{"Гуырдзыстон"}
|
| D | zh_Hant_HK.txt | 36 GE{"格魯吉亞"}
|
| D | yi.txt | 92 GE{"גרוזיע"}
|
| /third_party/skia/third_party/externals/icu/source/data/region/ |
| D | os.txt | 17 GE{"Гуырдзыстон"}
|
| D | zh_Hant_HK.txt | 36 GE{"格魯吉亞"}
|
| D | yi.txt | 92 GE{"גרוזיע"}
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionOptimizer.cpp | 231 case AArch64CC::GT: return AArch64CC::GE; in getAdjustedCmp()
232 case AArch64CC::GE: return AArch64CC::GT; in getAdjustedCmp()
|
| D | AArch64SchedFalkorDetails.td | 588 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT))(v2f32|v2i32p)$")>;
589 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FAC(GE|GT)(32|64)$")>;
590 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
614 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(F(MAX|MIN)(NM)?P?|FAC(GE|GT)|FCM(EQ|GE|GT))(v2f…
615 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v2i64|v4i32)rz$")>;
669 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(…
670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
735 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v16i8|v2i64|v4i32|v8i16)$")>;
[all …]
|
| /third_party/lzma/Asm/x86/ |
| D | Sha256Opt.asm | 189 if (k GE (4 - pre1)) AND (k LT (16 - pre1))
196 if (k GE (4 - pre2)) AND (k LT (16 - pre2))
|
| /third_party/gn/src/base/ |
| D | logging.h | 563 DEFINE_CHECK_OP_IMPL(GE, >=)
571 #define CHECK_GE(val1, val2) CHECK_OP(GE, >=, val1, val2)
729 #define DCHECK_GE(val1, val2) DCHECK_OP(GE, >=, val1, val2)
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 246 GE = 0xa, // Greater than or equal Greater than or equal enumerator
275 case GE: return "ge"; in getCondCodeName()
309 case GE: return 0; // N == V in getNZCVToSatisfyCondCode()
|
| /third_party/vixl/test/aarch32/config/ |
| D | cond-rd-rn-rm-a32.json | 30 // The instructions covered in this test do not write to the `Q` and `GE` flags,
77 // Instructions affecting the GE bits.
|
| D | cond-rd-rn-rm-t32.json | 30 // The instructions covered in this test do not write to the `Q` and `GE` flags,
76 // Instructions affecting the GE bits.
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.cpp | 116 case ARCCC::GE: in GetOppositeBranchCondition()
123 return ARCCC::GE; in GetOppositeBranchCondition()
|