| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 290 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
291 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
293 HasBaseReg = false; in PrintLeaMemReference()
296 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
321 if (HasBaseReg) in PrintLeaMemReference()
357 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
358 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
360 HasBaseReg = false; in PrintIntelMemReference()
371 if (HasBaseReg) { in PrintIntelMemReference()
389 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
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| D | X86ISelLowering.cpp | 29980 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
30002 if (AM.HasBaseReg) in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 332 bool HasBaseReg = false; member
452 HasBaseReg = true; in initialMatch()
458 HasBaseReg = true; in initialMatch()
602 if (HasBaseReg && BaseRegs.empty()) { in print()
605 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1213 bool HasBaseReg, int64_t Scale,
1378 Offset, F.HasBaseReg, F.Scale, Fixup.UserInst)) in RateFormula()
1632 bool HasBaseReg, int64_t Scale, in isAMCompletelyFolded() argument
1637 HasBaseReg, Scale, AccessTy.AddrSpace, Fixup); in isAMCompletelyFolded()
1646 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isAMCompletelyFolded()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 231 bool HasBaseReg, int64_t Scale,
294 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
296 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
755 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
799 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, in getGEPCost()
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| D | TargetTransformInfo.h | 562 bool HasBaseReg, int64_t Scale,
633 bool HasBaseReg, int64_t Scale,
1224 int64_t BaseOffset, bool HasBaseReg,
1248 int64_t BaseOffset, bool HasBaseReg,
1503 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
1506 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
1562 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
1564 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | BasicTTIImpl.h | 238 bool HasBaseReg, int64_t Scale,
243 AM.HasBaseReg = HasBaseReg;
265 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
269 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
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| D | TargetLowering.h | 2170 bool HasBaseReg = false; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 268 bool HasBaseReg, in isLegalAddressingMode() argument
272 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
351 bool HasBaseReg, in getScalingFactorCost() argument
354 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPerfHintAnalysis.cpp | 245 AM.HasBaseReg = !AM.BaseGV; in visit()
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| D | SILoadStoreOptimizer.cpp | 1841 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
1866 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
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| D | SIISelLowering.cpp | 1140 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1198 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1217 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
8100 AM.HasBaseReg = true; in performSHLPtrCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 3254 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4323 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4328 AddrMode.HasBaseReg = true; in matchOperationAddr()
4339 if (AddrMode.HasBaseReg) in matchOperationAddr()
4341 AddrMode.HasBaseReg = true; in matchOperationAddr()
4474 if (!AddrMode.HasBaseReg) { in matchAddr()
4475 AddrMode.HasBaseReg = true; in matchAddr()
4480 AddrMode.HasBaseReg = false; in matchAddr()
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| D | TargetLoweringBase.cpp | 1751 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1756 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 750 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
762 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 4230 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4237 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1893 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 283 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 15238 if (!AM.HasBaseReg && Scale == 2) in isLegalT2ScaledAddressingMode()
15264 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); in isLegalT1ScaledAddressingMode()
15311 if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) in isLegalAddressingMode()
15314 if (!AM.HasBaseReg && Scale == 2) in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 4255 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 927 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
13706 AM.HasBaseReg = true; in canFoldInAddressingMode()
13715 AM.HasBaseReg = true; in canFoldInAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 14816 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
14821 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9479 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
|