Searched refs:Hwreg (Results 1 – 13 of 13) sorted by relevance
200 .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) | in insertSetreg()201 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) | in insertSetreg()202 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_)); in insertSetreg()246 if (((Dst & AMDGPU::Hwreg::ID_MASK_) >> AMDGPU::Hwreg::ID_SHIFT_) != in processBlockPhase1()247 AMDGPU::Hwreg::ID_MODE) in processBlockPhase1()250 unsigned Width = ((Dst & AMDGPU::Hwreg::WIDTH_M1_MASK_) >> in processBlockPhase1()251 AMDGPU::Hwreg::WIDTH_M1_SHIFT_) + in processBlockPhase1()254 (Dst & AMDGPU::Hwreg::OFFSET_MASK_) >> AMDGPU::Hwreg::OFFSET_SHIFT_; in processBlockPhase1()
1194 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE : in getSegmentAperture()1195 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE; in getSegmentAperture()1197 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE : in getSegmentAperture()1198 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE; in getSegmentAperture()1200 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ | in getSegmentAperture()1201 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ | in getSegmentAperture()1202 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_; in getSegmentAperture()2052 unsigned SPDenormModeBitField = AMDGPU::Hwreg::ID_MODE | in toggleSPDenormMode()2053 (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) | in toggleSPDenormMode()2054 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_); in toggleSPDenormMode()
232 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_LO | in emitFlatScratchInit()233 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitFlatScratchInit()236 addImm(int16_t(AMDGPU::Hwreg::ID_FLAT_SCR_HI | in emitFlatScratchInit()237 (31 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_))); in emitFlatScratchInit()
313 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
128 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_; in getHWReg()815 return getHWReg(TII, *MI) == AMDGPU::Hwreg::ID_TRAPSTS; in checkRFEHazards()
3139 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg( in emitGWSMemViolTestLoop()3140 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1); in emitGWSMemViolTestLoop()4678 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE : in getSegmentAperture()4679 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE; in getSegmentAperture()4681 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE : in getSegmentAperture()4682 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE; in getSegmentAperture()4684 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ | in getSegmentAperture()4685 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ | in getSegmentAperture()4686 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_; in getSegmentAperture()7726 const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE | in LowerFDIV32()[all …]
1102 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
22 namespace Hwreg { // Symbolic names for the hwreg(...) syntax.
52 namespace Hwreg { namespace
459 namespace Hwreg {
710 namespace Hwreg { namespace
1316 using namespace llvm::AMDGPU::Hwreg; in printHwreg()
4994 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()5023 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()5043 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()