| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 76 InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); in runOnMachineFunction() local
78 assert(ISel && "Cannot work without InstructionSelector"); in runOnMachineFunction()
79 ISel->setupMF(MF, KB, CoverageInfo); in runOnMachineFunction()
135 if (!ISel->select(MI)) { in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 807 HexagonDAGToDAGISel &ISel; member
813 : Lower(getHexagonLowering(G)), ISel(HS), DAG(G), in HvxSelector()
973 ISel.Select(L); in selectVectorConstants()
999 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
1035 ISel.ReplaceNode(InpN, OutN); in materialize()
1394 Ops.push_back(ISel.selectUndef(dl, LegalTy)); in scalarizeShuffle()
1437 ISel.ReplaceNode(N, LV.getNode()); in scalarizeShuffle()
1486 ISel.Select(S); in scalarizeShuffle()
2044 ISel.ReplaceNode(N, ISel.selectUndef(SDLoc(SN), ResTy).getNode()); in selectShuffle()
2099 ISel.ReplaceNode(N, NewN); in selectRor()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 50 TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State, in executeMatchTable() argument
600 (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])( in executeMatchTable()
955 (ISel.*ISelInfo.CustomRenderers[RendererFnID])( in executeMatchTable()
973 (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID], in executeMatchTable()
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| D | InstructionSelector.h | 461 TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFormats.td | 46 // instructions are used for ISel and all MI passes. The stack versions of the
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Relocation.txt | 37 to ISel which in turn relies on TableGen patterns to choose subtarget
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| D | MSA.txt | 5 optimisation, reduce the size of the ISel matcher, and reduce repetition in
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| D | MipsMSAInstrInfo.td | 357 // ISel generator requires the uses to have a name, but providing a name
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 1625 // different to how ISel expects them for a post-inc load, so use a pseudo
1626 // and expand it just after ISel.
1635 // multiple registers) is the same in ISel as MachineInstr, so there's no need
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| D | ARMInstrMVE.td | 283 // ISel patterns.
287 // of those in Vec, so we can use it in ISel patterns. It is up to the
292 // predicate bits, for use in ISel patterns that handle an IR
5285 // Multiclasses wrapping that to add ISel patterns for intrinsics.
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| D | ARMInstrFormats.td | 191 // Transform to generate the inverse of a condition code during ISel
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| D | ARMInstrInfo.td | 3063 // put the patterns on the instruction definitions directly as ISel wants
3968 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
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| D | ARMInstrThumb2.td | 1694 // put the patterns on the instruction definitions directly as ISel wants
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | TargetOpcodes.def | 199 /// The following generic opcodes are not supposed to appear after ISel.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGISel.cpp | 215 OptLevelChanger(SelectionDAGISel &ISel, in OptLevelChanger() argument
216 CodeGenOpt::Level NewOptLevel) : IS(ISel) { in OptLevelChanger()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 21 // and return value are essentially chains, used to force ordering during ISel.
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| D | IntrinsicsAArch64.td | 54 // ordering during ISel.
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| /third_party/vk-gl-cts/external/vulkancts/data/vulkan/amber/graphicsfuzz/ |
| D | index.txt | 599 …el-lowering-machine-value-type-uint-to-float", "Covers specific X86 ISel lowering and machin…
600 …ring-selection-dag-struct-array-clamp-index", "Covers a specific X86 ISel lowering and DAG se…
601 …loat-nan-cos-cos", "A fragment shader that covers a specific X86 ISel lowering and AP Flo…
602 …ative-left-shift", "A fragment shader that covers a specific X86 ISel lowering code path"…
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 1611 // Pull in the common support for Global ISel register bank info generation.
1621 // Pull in the common support for the Global ISel DAG-based selector generation.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600Instructions.td | 1722 // ISel Patterns
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 1021 // because we also need to be able to specify a pattern to match for ISel.
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 1290 // the instruction definitions directly as ISel wants the address base
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| D | PPCInstrInfo.td | 2166 // the instruction definitions directly as ISel wants the address base
2254 // the instruction definitions directly as ISel wants the address base
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.td | 1819 // bt instruction does not ignore the high bits of the index. From ISel's
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| D | X86InstrAVX512.td | 174 // It assumes custom ISel patterns for masking which can be provided as
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