Searched refs:IdxReg (Results 1 – 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1176 Register IdxReg = MRI.createGenericVirtualRegister(LLT::scalar(32)); in applyMappingWideLoad() local
1177 B.buildConstant(IdxReg, DefIdx); in applyMappingWideLoad()
1178 MRI.setRegBank(IdxReg, AMDGPU::VGPRRegBank); in applyMappingWideLoad()
1179 B.buildExtractVectorElement(DefRegs[DefIdx], TmpReg, IdxReg); in applyMappingWideLoad()
1948 Register IdxReg = MI.getOperand(2).getReg(); in applyMappingImpl() local
1991 auto IdxLo = B.buildShl(S32, IdxReg, One); in applyMappingImpl()
2050 Register IdxReg = MI.getOperand(3).getReg(); in applyMappingImpl() local
2071 auto IdxLo = B.buildShl(S32, IdxReg, One); in applyMappingImpl()
3020 Register IdxReg = MI.getOperand(3).getReg(); in getInstrMapping() local
3021 unsigned IdxSize = MRI.getType(IdxReg).getSizeInBits(); in getInstrMapping()
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| D | AMDGPUInstructionSelector.cpp | 1699 Register IdxReg = MI.getOperand(2).getReg(); in selectG_EXTRACT_VECTOR_ELT() local
1706 const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
1719 !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_EXTRACT_VECTOR_ELT()
1733 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
1748 .addReg(IdxReg); in selectG_EXTRACT_VECTOR_ELT()
1757 .addReg(IdxReg) in selectG_EXTRACT_VECTOR_ELT()
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| D | SIISelLowering.cpp | 3176 const MachineOperand &IdxReg, in emitLoadM0FromVGPRLoop() argument
3209 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef())); in emitLoadM0FromVGPRLoop()
3214 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg()); in emitLoadM0FromVGPRLoop()
3225 unsigned IdxReg; in emitLoadM0FromVGPRLoop() local
3227 IdxReg = CurrentIdxReg; in emitLoadM0FromVGPRLoop()
3229 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in emitLoadM0FromVGPRLoop()
3230 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg) in emitLoadM0FromVGPRLoop()
3238 .addReg(IdxReg, RegState::Kill) in emitLoadM0FromVGPRLoop()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMConstantIslandPass.cpp | 2207 unsigned IdxReg = ~0U; in optimizeThumb2JumpTables() local
2210 IdxReg = MI->getOperand(1).getReg(); in optimizeThumb2JumpTables()
2231 IdxReg = Shift->getOperand(2).getReg(); in optimizeThumb2JumpTables()
2237 if (BaseReg == IdxReg && !jumpTableFollowsTB(MI, User.CPEMI)) in optimizeThumb2JumpTables()
2268 if (registerDefinedBetween(IdxReg, Add->getNextNode(), MI, TRI)) in optimizeThumb2JumpTables()
2276 if (registerDefinedBetween(IdxReg, Load->getNextNode(), MI, TRI)) in optimizeThumb2JumpTables()
2299 .addReg(IdxReg, getKillRegState(IdxRegKill)) in optimizeThumb2JumpTables()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | IRTranslator.cpp | 1093 Register IdxReg = getOrCreateVReg(*Idx); in translateGetElementPtr() local
1094 if (MRI->getType(IdxReg) != OffsetTy) in translateGetElementPtr()
1095 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0); in translateGetElementPtr()
1104 MIRBuilder.buildMul(OffsetTy, ElementSizeMIB, IdxReg).getReg(0); in translateGetElementPtr()
1106 GepOffsetReg = IdxReg; in translateGetElementPtr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 3913 Register IdxReg = I.getOperand(3).getReg(); in selectInsertElt() local
3914 auto VRegAndVal = getConstantVRegValWithLookThrough(IdxReg, MRI); in selectInsertElt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 847 AddressingMode(bool LongDispl, bool IdxReg) : in AddressingMode()
848 LongDisplacement(LongDispl), IndexReg(IdxReg) {} in AddressingMode()
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