| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 2204 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in PPCMaterializeInt() local
2206 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg); in PPCMaterializeInt()
2207 return ImmReg; in PPCMaterializeInt()
2224 unsigned ImmReg = createResultReg(RC); in PPCMaterializeInt() local
2225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg) in PPCMaterializeInt()
2227 return ImmReg; in PPCMaterializeInt()
2386 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass); in fastEmit_i() local
2388 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg); in fastEmit_i()
2389 return ImmReg; in fastEmit_i()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 992 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair() local
993 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1000 .addReg(ImmReg) in mergeRead2Pair()
1085 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair() local
1086 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1093 .addReg(ImmReg) in mergeWrite2Pair()
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| D | R600ISelLowering.cpp | 2153 unsigned ImmReg = R600::ALU_LITERAL_X; in FoldOperand() local
2160 ImmReg = R600::ZERO; in FoldOperand()
2162 ImmReg = R600::HALF; in FoldOperand()
2164 ImmReg = R600::ONE; in FoldOperand()
2172 ImmReg = R600::ZERO; in FoldOperand()
2174 ImmReg = R600::ONE_INT; in FoldOperand()
2183 if (ImmReg == R600::ALU_LITERAL_X) { in FoldOperand()
2192 Src = DAG.getRegister(ImmReg, MVT::i32); in FoldOperand()
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| D | AMDGPUInstructionSelector.cpp | 1662 Register ImmReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
1663 BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg) in selectG_PTR_MASK()
1669 .addReg(ImmReg); in selectG_PTR_MASK()
1685 .addReg(ImmReg); in selectG_PTR_MASK()
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| D | SIInstrInfo.cpp | 5672 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
5677 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
5681 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
5691 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
5692 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
5695 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
5701 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in movePackToVALU() local
5706 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
5710 .addReg(ImmReg, RegState::Kill) in movePackToVALU()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 475 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
477 TII.get(Opc), ImmReg) in ARMMaterializeInt()
479 return ImmReg; in ARMMaterializeInt()
491 unsigned ImmReg = createResultReg(RC); in ARMMaterializeInt() local
493 TII.get(Opc), ImmReg) in ARMMaterializeInt()
495 return ImmReg; in ARMMaterializeInt()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitSimplify.cpp | 1479 unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL); in processBlock() local
1480 if (ImmReg) { in processBlock()
1481 HBS::replaceReg(DR, ImmReg, MRI); in processBlock()
1482 BT.put(ImmReg, DRC); in processBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4573 unsigned ImmReg = DstReg; in expandSgeImm() local
4578 ImmReg = ATReg; in expandSgeImm()
4581 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgeImm()
4585 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4603 unsigned ImmReg = DstReg; in expandSgtImm() local
4626 ImmReg = ATReg; in expandSgtImm()
4629 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), in expandSgtImm()
4634 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
|