| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 555 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
577 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
596 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchSetup()
619 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
635 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
646 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
650 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
656 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
660 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
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| D | SILowerControlFlow.cpp | 221 .addReg(Exec, RegState::ImplicitDefine); in emitIf()
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| D | SIRegisterInfo.cpp | 900 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR()
930 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in restoreSGPR()
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| D | SIISelLowering.cpp | 3533 .addReg(Dst, RegState::ImplicitDefine) in emitIndirectDst()
3567 .addReg(Dst, RegState::ImplicitDefine) in emitIndirectDst()
3810 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine) in EmitInstrWithCustomInserter()
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| D | SIInstrInfo.cpp | 1500 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 236 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
678 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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| D | SystemZShortenInst.cpp | 146 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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| D | SystemZFrameLowering.cpp | 350 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| D | SystemZInstrInfo.cpp | 223 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 54 ImplicitDefine = Implicit | Define, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
737 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1611 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| D | Thumb2InstrInfo.cpp | 214 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMFrameLowering.cpp | 1379 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1396 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
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| D | ARMBaseInstrInfo.cpp | 1340 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1386 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1410 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1430 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMLoadStoreOptimizer.cpp | 956 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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| D | ARMISelLowering.cpp | 10003 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 2143 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2144 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
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| D | MipsSEInstrInfo.cpp | 134 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| D | MipsSEISelDAGToDAG.cpp | 57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 903 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4108 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4137 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4212 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
4585 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
4594 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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| D | X86ISelLowering.cpp | 31157 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
31165 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
31173 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
31314 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
31326 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
31338 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
32203 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 1338 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2296 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
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