Searched refs:InputInt5 (Results 1 – 7 of 7) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | code-generator-arm64.cc | 118 return Operand(InputRegister32(index), LSL, InputInt5(index + 1)); in InputOperand2_32()
120 return Operand(InputRegister32(index), LSR, InputInt5(index + 1)); in InputOperand2_32()
122 return Operand(InputRegister32(index), ASR, InputInt5(index + 1)); in InputOperand2_32()
124 return Operand(InputRegister32(index), ROR, InputInt5(index + 1)); in InputOperand2_32()
1465 __ Sbfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1), in AssembleArchInstruction()
1466 i.InputInt5(2)); in AssembleArchInstruction()
1473 __ Ubfx(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1), in AssembleArchInstruction()
1477 __ Ubfiz(i.OutputRegister32(), i.InputRegister32(0), i.InputInt5(1), in AssembleArchInstruction()
1478 i.InputInt5(2)); in AssembleArchInstruction()
2891 __ Tbz(i.InputRegister32(0), i.InputInt5(1), tlabel); in AssembleArchBranch()
[all …]
|
| /third_party/node/deps/v8/src/compiler/backend/ |
| D | code-generator-impl.h | 81 uint8_t InputInt5(size_t index) { in InputInt5() function
|
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| D | code-generator-riscv64.cc | 2129 i.InputInt5(1)); in AssembleArchInstruction()
2269 i.InputInt5(1) % 8); in AssembleArchInstruction()
2281 i.InputInt5(1) % 16); in AssembleArchInstruction()
2321 i.InputInt5(1) % 32); in AssembleArchInstruction()
2351 i.InputInt5(1) % 8); in AssembleArchInstruction()
2363 i.InputInt5(1) % 16); in AssembleArchInstruction()
2375 i.InputInt5(1) % 32); in AssembleArchInstruction()
2561 i.InputInt5(1) % 8); in AssembleArchInstruction()
2573 i.InputInt5(1) % 16); in AssembleArchInstruction()
2585 i.InputInt5(1) % 32); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | code-generator-ia32.cc | 1133 __ shl(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction()
1140 __ shr(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction()
1147 __ sar(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction()
1240 __ rol(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction()
1247 __ ror(i.OutputOperand(), i.InputInt5(1)); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| D | code-generator-arm.cc | 67 return Operand(InputRegister(index + 0), ASR, InputInt5(index + 1)); in InputOperand2()
71 return Operand(InputRegister(index + 0), LSL, InputInt5(index + 1)); in InputOperand2()
75 return Operand(InputRegister(index + 0), LSR, InputInt5(index + 1)); in InputOperand2()
79 return Operand(InputRegister(index + 0), ROR, InputInt5(index + 1)); in InputOperand2()
|
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| D | code-generator-mips64.cc | 2541 i.InputInt5(1)); in AssembleArchInstruction()
2553 i.InputInt5(1)); in AssembleArchInstruction()
2565 i.InputInt5(1)); in AssembleArchInstruction()
|
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| D | code-generator-mips.cc | 2442 i.InputInt5(1)); in AssembleArchInstruction()
2448 i.InputInt5(1)); in AssembleArchInstruction()
2454 i.InputInt5(1)); in AssembleArchInstruction()
|