| /third_party/node/deps/v8/src/compiler/backend/ |
| D | register-allocator-verifier.cc | 181 if (sequence()->IsFP(vreg)) { in BuildConstraint()
188 DCHECK(!sequence()->IsFP(vreg)); in BuildConstraint()
205 if (sequence()->IsFP(vreg)) { in BuildConstraint()
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| D | instruction.h | 1694 bool IsFP(int virtual_register) const { in NON_EXPORTED_BASE()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.h | 112 bool IsFP) const;
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| D | MipsSEISelLowering.cpp | 3328 bool IsFP) const { in emitINSERT_DF_VIDX()
3375 if (IsFP) { in emitINSERT_DF_VIDX()
3401 if (IsFP) { in emitINSERT_DF_VIDX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Bitcode/Reader/ |
| D | BitcodeReader.cpp | 1059 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedUnaryOpcode() local
1061 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedUnaryOpcode()
1068 return IsFP ? Instruction::FNeg : -1; in getDecodedUnaryOpcode()
1073 bool IsFP = Ty->isFPOrFPVectorTy(); in getDecodedBinaryOpcode() local
1075 if (!IsFP && !Ty->isIntOrIntVectorTy()) in getDecodedBinaryOpcode()
1082 return IsFP ? Instruction::FAdd : Instruction::Add; in getDecodedBinaryOpcode()
1084 return IsFP ? Instruction::FSub : Instruction::Sub; in getDecodedBinaryOpcode()
1086 return IsFP ? Instruction::FMul : Instruction::Mul; in getDecodedBinaryOpcode()
1088 return IsFP ? -1 : Instruction::UDiv; in getDecodedBinaryOpcode()
1090 return IsFP ? Instruction::FDiv : Instruction::SDiv; in getDecodedBinaryOpcode()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 424 unsigned MachineIRBuilder::getBoolExtOp(bool IsVec, bool IsFP) const { in getBoolExtOp()
426 switch (TLI->getBooleanContents(IsVec, IsFP)) { in getBoolExtOp()
438 bool IsFP) { in buildBoolExt() argument
439 unsigned ExtOp = getBoolExtOp(getMRI()->getType(Op.getReg()).isVector(), IsFP); in buildBoolExt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1031 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/AsmParser/ |
| D | LLParser.h | 579 bool IsFP);
581 bool IsFP);
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| D | LLParser.cpp | 6336 unsigned Opc, bool IsFP) { in ParseUnaryOp() argument
6341 bool Valid = IsFP ? LHS->getType()->isFPOrFPVectorTy() in ParseUnaryOp()
6479 unsigned Opc, bool IsFP) { in ParseArithmetic() argument
6486 bool Valid = IsFP ? LHS->getType()->isFPOrFPVectorTy() in ParseArithmetic()
7104 bool IsFP = false; in ParseAtomicRMW() local
7125 IsFP = true; in ParseAtomicRMW()
7129 IsFP = true; in ParseAtomicRMW()
7154 } else if (IsFP) { in ParseAtomicRMW()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 550 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
555 bool IsFP);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 862 bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() != in selectSelectOpc() local
866 return IsFP ? AArch64::FCSELSrrr : AArch64::CSELWr; in selectSelectOpc()
868 return IsFP ? AArch64::FCSELDrrr : AArch64::CSELXr; in selectSelectOpc()
3713 bool IsFP = ScalarRB->getID() == AArch64::FPRRegBankID; in tryOptVectorDup() local
3715 if (IsFP) { in tryOptVectorDup()
3749 if (IsFP) { in tryOptVectorDup()
3757 if (IsFP) in tryOptVectorDup()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1278 bool IsFP = fieldFromInstruction(insn, 26, 1); in DecodeSignedLdStInstruction() local
1281 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2787 bool IsFP = CmpOp0.getValueType().isFloatingPoint(); in lowerVectorSETCC() local
2788 assert (!Chain || IsFP); in lowerVectorSETCC()
2791 Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int; in lowerVectorSETCC()
2800 assert(IsFP && "Unexpected integer comparison"); in lowerVectorSETCC()
2817 assert(IsFP && "Unexpected integer comparison"); in lowerVectorSETCC()
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| D | instruction-selector-ia32.cc | 1475 sequence()->IsFP(GetVirtualRegister(input.node))) { in EmitPrepareArguments()
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| D | instruction-selector-x64.cc | 1976 sequence()->IsFP(GetVirtualRegister(input.node))) { in EmitPrepareArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 334 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
337 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20347 bool IsFP = Op.getSimpleValueType().isFloatingPoint(); in lowerAddSubToHorizontalOp() local
20348 if (IsFP && !Subtarget.hasSSE3()) in lowerAddSubToHorizontalOp()
20350 if (!IsFP && !Subtarget.hasSSSE3()) in lowerAddSubToHorizontalOp()
21876 bool IsFP = Op1.getSimpleValueType().isFloatingPoint(); in emitFlagsForSetcc() local
21877 X86::CondCode CondCode = TranslateX86CC(CC, dl, IsFP, Op0, Op1, DAG); in emitFlagsForSetcc()
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