| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 32 class MCOperand; variable
60 MCOperand createRegOperand(unsigned int RegId) const;
61 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
62 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
64 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
73 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
74 MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
76 MCOperand decodeOperand_VS_32(unsigned Val) const;
77 MCOperand decodeOperand_VS_64(unsigned Val) const;
78 MCOperand decodeOperand_VS_128(unsigned Val) const;
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| D | AMDGPUDisassembler.cpp | 72 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, in insertNamedMCOperand()
101 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSoppBrTarget()
369 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
410 MCOperand::createReg(MI.getOperand(Tied).getReg()), in getInstruction()
427 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); in convertSDWAInst()
436 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); in convertSDWAInst()
449 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertDPP8Inst()
454 insertNamedMCOperand(MI, MCOperand::createImm(0), in convertDPP8Inst()
574 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); in convertMIMGInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 16 MCOperand MCOp;
32 MCOperand MCOp;
48 MCOperand MCOp;
64 MCOperand MCOp;
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
78 MCOperand MCOp;
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
90 MCOperand MCOp;
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInst.h | 34 class MCOperand {
54 MCOperand() : FPImmVal(0.0) {} in MCOperand() function
115 static MCOperand createReg(unsigned Reg) { in createReg()
116 MCOperand Op; in createReg()
122 static MCOperand createImm(int64_t Val) { in createImm()
123 MCOperand Op; in createImm()
129 static MCOperand createFPImm(double Val) { in createFPImm()
130 MCOperand Op; in createFPImm()
136 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
137 MCOperand Op; in createExpr()
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| D | MCInstBuilder.h | 32 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
38 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
44 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
50 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
56 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
61 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 73 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
78 return MCOperand::createExpr(expr); in createSparcMCOperand()
81 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
86 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
101 return MCOperand::createExpr(expr); in createPCXRelExprOp()
105 MCOperand &Callee, in EmitCall()
115 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
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| D | SparcMCInstLower.cpp | 29 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
64 return MCOperand::createExpr(expr); in LowerSymbolOperand()
67 static MCOperand LowerOperand(const MachineInstr *MI, in LowerOperand()
75 return MCOperand::createReg(MO.getReg()); in LowerOperand()
78 return MCOperand::createImm(MO.getImm()); in LowerOperand()
90 return MCOperand(); in LowerOperand()
102 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerSparcMachineInstrToMCInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 16 MCOperand MCOp;
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
29 MCOperand MCOp;
54 MCOperand MCOp;
81 MCOperand MCOp;
84 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
89 TmpInst.addOperand(MCOperand::createImm(14));
90 TmpInst.addOperand(MCOperand::createReg(0));
92 TmpInst.addOperand(MCOperand::createReg(0));
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonAsmPrinter.cpp | 181 MCStreamer &OutStreamer, const MCOperand &Imm, in smallData()
255 MCOperand &ImmOp = Inst.getOperand(i); in ScaleVectorOffset()
260 T.addOperand(MCOperand::createExpr(NewHE)); in ScaleVectorOffset()
279 MCOperand Reg = Inst.getOperand(0); in HexagonProcessInstruction()
280 MCOperand S16 = Inst.getOperand(1); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
293 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
300 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
307 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
314 Inst.addOperand(MCOperand::createExpr(Zero)); in HexagonProcessInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 67 Inst.addOperand(MCOperand::createImm(Offset)); in DecodePCRel24BranchTarget()
78 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
182 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
190 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
213 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
220 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
224 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); in decodeMemRIOperands()
225 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
241 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
243 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 415 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
420 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
425 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
430 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
449 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
454 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
459 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
464 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
469 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
474 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 100 const MCOperand &Dst = MI->getOperand(0); in printInst()
101 const MCOperand &MO1 = MI->getOperand(1); in printInst()
102 const MCOperand &MO2 = MI->getOperand(2); in printInst()
103 const MCOperand &MO3 = MI->getOperand(3); in printInst()
123 const MCOperand &Dst = MI->getOperand(0); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst()
267 MCOperand NewReg; in printInst()
272 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( in printInst()
313 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
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| D | ARMMCCodeEmitter.cpp | 86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
317 const MCOperand &MO = MI.getOperand(Op); in getModImmOpValue()
336 const MCOperand &MO = MI.getOperand(Op); in getT2SOImmOpValue()
421 const MCOperand MO = MI.getOperand(Op); in getExpandedImmOpValue()
560 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
600 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
601 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
630 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
667 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
680 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 380 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
385 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
394 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
404 Inst.addOperand(MCOperand::createExpr(NewExpr)); in addSignedImmOperands()
534 for (MCOperand &I : MCI) in canonicalizeImmediates()
537 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
613 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
646 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
1223 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst()
1224 MCOperand &MO2) { in makeCombineInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
174 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
256 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
297 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
318 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
201 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
215 const MCOperand &MO = MI.getOperand(OpIdx); in getLdStUImm12OpValue()
236 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrLabelOpValue()
263 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue()
298 const MCOperand &MO = MI.getOperand(OpIdx); in getCondBranchTargetOpValue()
320 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLiteralOpValue()
349 const MCOperand &MO = MI.getOperand(OpIdx); in getMoveWideImmOpValue()
368 const MCOperand &MO = MI.getOperand(OpIdx); in getTestBranchTargetOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiInstPrinter.cpp | 152 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
165 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
179 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
191 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
203 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
214 const MCOperand &RegOp) { in printMemoryBaseRegister()
227 const MCOperand &OffsetOp, in printMemoryImmediateOffset()
240 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
241 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemRiOperand()
242 const MCOperand &AluOp = MI->getOperand(OpNo + 2); in printMemRiOperand()
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| D | LanaiMCCodeEmitter.cpp | 57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
110 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
137 const MCOperand AluOp = Inst.getOperand(3); in adjustPqBits()
142 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits()
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue()
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2); in getRiMemoryOpValue()
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue()
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue()
223 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2); in getRrMemoryOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 46 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
58 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
71 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
84 const MCOperand &MO = MI.getOperand(OpNo); in getAbsCondBrEncoding()
96 const MCOperand &MO = MI.getOperand(OpNo); in getImm16Encoding()
113 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIEncoding()
131 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIXEncoding()
149 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIX16Encoding()
171 const MCOperand &MO = MI.getOperand(OpNo); in getSPE8DisEncoding()
186 const MCOperand &MO = MI.getOperand(OpNo); in getSPE4DisEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VEMCInstLower.cpp | 27 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
32 return MCOperand::createExpr(MCSym); in LowerSymbolOperand()
35 static MCOperand LowerOperand(const MachineInstr *MI, const MachineOperand &MO, in LowerOperand()
44 return MCOperand::createReg(MO.getReg()); in LowerOperand()
47 return MCOperand::createImm(MO.getImm()); in LowerOperand()
55 return MCOperand(); in LowerOperand()
64 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerVEMachineInstrToMCInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
187 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
199 TmpInst.addOperand(MCOperand::createImm(Imm1)); in emitII()
200 TmpInst.addOperand(MCOperand::createImm(Imm2)); in emitII()
206 MCOperand Op2, SMLoc IDLoc, in emitRRX()
210 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
211 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreMCInstLower.cpp | 31 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
67 return MCOperand::createExpr(MCSym); in LowerSymbolOperand()
74 return MCOperand::createExpr(Add); in LowerSymbolOperand()
77 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
86 return MCOperand::createReg(MO.getReg()); in LowerOperand()
88 return MCOperand::createImm(MO.getImm() + offset); in LowerOperand()
100 return MCOperand(); in LowerOperand()
108 MCOperand MCOp = LowerOperand(MO); in Lower()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64MCInstLower.h | 20 class MCOperand; variable
37 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
40 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
42 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
44 MCOperand lowerSymbolOperandCOFF(const MachineOperand &MO,
46 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
834 CCI = MI.insert(CCI, MCOperand::createImm(CC)); in AddThumbPredicate()
837 MI.insert(CCI, MCOperand::createReg(0)); in AddThumbPredicate()
839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
851 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); in AddThumbPredicate()
854 MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
856 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
1133 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1147 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
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