Searched refs:MCR (Results 1 – 22 of 22) sorted by relevance
5905 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];5907 makeArrayRef(MCR.begin(), MCR.getNumRegs()),5923 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];5925 makeArrayRef(MCR.begin(), MCR.getNumRegs()),5942 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];5944 makeArrayRef(MCR.begin(), MCR.getNumRegs()),5961 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];5963 makeArrayRef(MCR.begin(), MCR.getNumRegs()),5979 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRRegClassID];5981 makeArrayRef(MCR.begin(), MCR.getNumRegs()),[all …]
1454 808570991U, // MCR5678 74531720U, // MCR9233 // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, MVE_UQRSHLL, MVE_VMOV...10333 // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,...10947 // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ...11139 // MCR, MCRR, t2MCR, t2MCR2, t2MCRR, t2MCRR211290 // MCR, t2MCR, t2MCR2
762 UINT64_C(234881040), // MCR15814 case ARM::MCR: {17437 CEFBS_IsARM, // MCR = 749
10779 …{ 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__i…10781 …{ 659 /* mcr */, ARM::MCR, Convert__CoprocNum1_1__Imm0_71_2__Reg1_3__CoprocReg1_4__CoprocReg1_5__I…
31440 /* 67232*/ OPC_MorphNodeTo0, TARGET_VAL(ARM::MCR), 0|OPFL_Chain,31443 …// Dst: (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i3…48690 /*105784*/ OPC_MorphNodeTo0, TARGET_VAL(ARM::MCR), 0|OPFL_Chain,48693 …// Dst: (MCR 15:{ *:[i32] }, 0:{ *:[i32] }, GPR:{ *:[i32] }:$zero, 7:{ *:[i32] }, 10:{ *:[i32] }, …
764 MCR = 749,6595 …cts), 0x100ULL, nullptr, nullptr, OperandInfo165, -1 ,&getMCRDeprecationInfo }, // Inst #749 = MCR
32222 … *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):…32223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MCR,
1929 /* 603 */ MCD::OPC_Decode, 237, 5, 94, // Opcode: MCR
250 MCR("Moose Cree", "crm"), enumConstant
4278 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];4280 makeArrayRef(MCR.begin(), MCR.getNumRegs()),4294 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];4296 makeArrayRef(MCR.begin(), MCR.getNumRegs()),4310 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];4312 makeArrayRef(MCR.begin(), MCR.getNumRegs()),4326 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];4328 makeArrayRef(MCR.begin(), MCR.getNumRegs()),4342 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];4344 makeArrayRef(MCR.begin(), MCR.getNumRegs()),[all …]
6812 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];6814 makeArrayRef(MCR.begin(), MCR.getNumRegs()),6826 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];6828 makeArrayRef(MCR.begin(), MCR.getNumRegs()),6840 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];6842 makeArrayRef(MCR.begin(), MCR.getNumRegs()),6854 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];6856 makeArrayRef(MCR.begin(), MCR.getNumRegs()),6868 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];6870 makeArrayRef(MCR.begin(), MCR.getNumRegs()),[all …]
4767 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];4769 makeArrayRef(MCR.begin(), MCR.getNumRegs()),4784 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];4786 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6260 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];6262 makeArrayRef(MCR.begin(), MCR.getNumRegs()),6276 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];6278 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5404 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,5410 ComplexDeprecationPredicate<"MCR">;5412 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,5902 // Pre-v7 uses MCR for synchronization barriers.5903 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
145 "(t2)?MCR(2|R|R2)?$", "(t2)?MRC(2)?$",
4794 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in tryWriteRegister()
16701 Function *MCR = Intrinsic::getDeclaration(M, Intrinsic::arm_mcr); in makeDMB() local16705 return Builder.CreateCall(MCR, args); in makeDMB()
4437 ComplexDeprecationPredicate<"MCR">;
1058 PIPE MCR $gen0$gen_args > \$@
1055 PIPE MCR $gen0$gen_args > \$@
744 …j�lA=8ac_V:QcQW�hbXR��>3\JC�?6T`g|�pd`�qD^i�CArC�E=:@�Q;7<�S:go�Z�sz�dFb��MCR�MNGb\OeD�NJ`RWRgy}F…
22536 generating errors as ARMv7-a expects the MCR/MRC instructions to