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Searched refs:MCSchedClassDesc (Results 1 – 25 of 26) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetSchedule.h47 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
60 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
103 const MCSchedClassDesc *SC = nullptr) const;
106 const MCSchedClassDesc *SC = nullptr) const;
110 const MCSchedClassDesc *SC = nullptr) const;
134 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
138 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
DMachineTraceMetrics.h66 struct MCSchedClassDesc;
288 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
289 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
DScheduleDAGInstrs.h44 struct MCSchedClassDesc;
265 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
DScheduleDAG.h39 struct MCSchedClassDesc;
253 const MCSchedClassDesc *SchedClass =
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetSchedule.cpp86 const MCSchedClassDesc *SC) const { in mustBeginGroup()
97 const MCSchedClassDesc *SC) const { in mustEndGroup()
108 const MCSchedClassDesc *SC) const { in getNumMicroOps()
132 const MCSchedClassDesc *TargetSchedModel::
136 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
229 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
256 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
282 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
312 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
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DMachineCombiner.cpp111 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
367 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
371 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
392 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
393 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
398 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC); in preservesResourceLen()
399 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC); in preservesResourceLen()
DMachineTraceMetrics.cpp122 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1226 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1227 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1234 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1238 for (const MCSchedClassDesc *SC : Instrs) { in getResourceLength()
DMachineScheduler.cpp1891 const MCSchedClassDesc *SC = DAG->getSchedClass(&SU); in init()
2014 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2219 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2456 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
DMachinePipeliner.cpp933 const MCSchedClassDesc *SCDesc = in minFuncUnits()
976 const MCSchedClassDesc *SCDesc = in calcCriticalResources()
2943 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in canReserveResources()
2983 const MCSchedClassDesc *SCDesc = SM.getSchedClassDesc(InsnClass); in reserveResources()
DScheduleDAGInstrs.cpp592 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCSchedule.h110 struct MCSchedClassDesc { struct
306 const MCSchedClassDesc *SchedClassTable;
346 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
355 const MCSchedClassDesc &SCDesc);
364 const MCSchedClassDesc &SCDesc);
DMCSubtargetInfo.h161 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
165 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
169 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
177 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
199 getReadAdvanceEntries(const MCSchedClassDesc &SC) const { in getReadAdvanceEntries()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCSchedule.cpp41 const MCSchedClassDesc &SCDesc) { in computeInstrLatency()
58 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
71 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
89 const MCSchedClassDesc &SCDesc) { in getReciprocalThroughput()
114 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp47 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
93 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
171 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
272 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
341 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
390 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
418 const MCSchedClassDesc *SC = SchedModel->resolveSchedClass(MI); in emitInstruction()
DSystemZHazardRecognizer.h121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
DSystemZMachineScheduler.cpp254 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
DInstrBuilder.cpp39 const MCSchedClassDesc &SCDesc, in initializeUsedResources()
204 const MCSchedClassDesc &SCDesc, in computeMaxLatency()
251 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in populateWrites()
535 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); in createInstrDescImpl()
536 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in createInstrDescImpl()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp86 const MCSchedClassDesc *SCDesc = in shouldAddSTPToBlock()
DAArch64SIMDInstrOpt.cpp228 const MCSchedClassDesc *SCDesc = in shouldReplaceInst()
233 const MCSchedClassDesc *SCDescRepl; in shouldReplaceInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp209 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
DRegisterFile.cpp418 const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID); in addRegisterRead()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc5688 static const llvm::MCSchedClassDesc AtomModelSchedClasses[] = {
7065 static const llvm::MCSchedClassDesc BdVer2ModelSchedClasses[] = {
8442 static const llvm::MCSchedClassDesc BroadwellModelSchedClasses[] = {
9819 static const llvm::MCSchedClassDesc BtVer2ModelSchedClasses[] = {
11196 static const llvm::MCSchedClassDesc SkylakeServerModelSchedClasses[] = {
12573 static const llvm::MCSchedClassDesc SandyBridgeModelSchedClasses[] = {
13950 static const llvm::MCSchedClassDesc HaswellModelSchedClasses[] = {
15327 static const llvm::MCSchedClassDesc SLMModelSchedClasses[] = {
16704 static const llvm::MCSchedClassDesc SkylakeClientModelSchedClasses[] = {
18081 static const llvm::MCSchedClassDesc Znver1ModelSchedClasses[] = {
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc1981 static const llvm::MCSchedClassDesc CycloneModelSchedClasses[] = {
3095 static const llvm::MCSchedClassDesc CortexA53ModelSchedClasses[] = {
4209 static const llvm::MCSchedClassDesc CortexA57ModelSchedClasses[] = {
5323 static const llvm::MCSchedClassDesc ExynosM3ModelSchedClasses[] = {
6437 static const llvm::MCSchedClassDesc ExynosM4ModelSchedClasses[] = {
7551 static const llvm::MCSchedClassDesc ExynosM5ModelSchedClasses[] = {
8665 static const llvm::MCSchedClassDesc FalkorModelSchedClasses[] = {
9779 static const llvm::MCSchedClassDesc KryoModelSchedClasses[] = {
10893 static const llvm::MCSchedClassDesc ThunderXT8XModelSchedClasses[] = {
12007 static const llvm::MCSchedClassDesc ThunderX2T99ModelSchedClasses[] = {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc259 static const llvm::MCSchedClassDesc MipsGenericModelSchedClasses[] = {
1943 static const llvm::MCSchedClassDesc MipsP5600ModelSchedClasses[] = {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc10747 static const llvm::MCSchedClassDesc CortexA9ModelSchedClasses[] = {
12196 static const llvm::MCSchedClassDesc CortexA57ModelSchedClasses[] = {
13645 static const llvm::MCSchedClassDesc CortexM4ModelSchedClasses[] = {
15094 static const llvm::MCSchedClassDesc CortexR52ModelSchedClasses[] = {
16543 static const llvm::MCSchedClassDesc SwiftModelSchedClasses[] = {

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