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Searched refs:MIs (Results 1 – 16 of 16) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
111 if ((size_t)NewInsnID < State.MIs.size()) in executeMatchTable()
112 State.MIs[NewInsnID] = NewMI; in executeMatchTable()
114 assert((size_t)NewInsnID == State.MIs.size() && in executeMatchTable()
116 State.MIs.push_back(NewMI); in executeMatchTable()
143 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
144 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
163 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
164 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
191 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
[all …]
DInstructionSelector.h423 RecordedMIVector MIs; member
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGICombiner.inc122 SmallVector<MachineInstr *, 8> MIs = { &MI };
133 switch (MIs[0]->getOpcode()) {
150 return Helper.matchCombineCopy(*MIs[0]);
153 Helper.applyCombineCopy(*MIs[0]);
165 return Helper.matchPtrAddImmedChain(*MIs[0], MatchData1);
168 Helper.applyPtrAddImmedChain(*MIs[0], MatchData1);
180 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2);
183 Helper.applyCombineExtendingLoads(*MIs[0], MatchData2);
192 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3);
195 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3);
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DAArch64GenGlobalISel.inc1131 State.MIs.clear();
1132 State.MIs.push_back(&I);
1363 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1369 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1372 // MIs[2] Rn
1388 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1394 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1397 // MIs[2] Rn
1427 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1431 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
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/third_party/openssl/test/
Ddanetest.in185 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
232 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
279 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
326 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
373 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
420 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
467 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
514 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
561 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
608 MIs/yHm9uKN6MHgwHQYDVR0OBBYEFFsgykF9kIjHpMAXy2wMHHObsH2KMB8GA1Ud
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp254 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
255 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
259 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
260 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
317 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
319 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
DR600InstrInfo.h143 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
DR600ControlFlowFinalizer.cpp495 void CounterPropagateAddr(const std::set<MachineInstr *> &MIs, in CounterPropagateAddr() argument
497 for (MachineInstr *MI : MIs) { in CounterPropagateAddr()
DR600InstrInfo.cpp608 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) in fitsConstReadLimitations()
612 for (unsigned i = 0, n = MIs.size(); i < n; i++) { in fitsConstReadLimitations()
613 MachineInstr &MI = *MIs[i]; in fitsConstReadLimitations()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc659 State.MIs.clear();
660 State.MIs.push_back(&I);
744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
749 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
752 // MIs[2] Operand 1
772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
777 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
780 // MIs[2] Operand 1
799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
802 // MIs[1] Operand 1
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DVirtRegMap.cpp407 SmallVector<MachineInstr *, 2> MIs({&MI}); in expandCopyBundle() local
416 MIs.push_back(&*I); in expandCopyBundle()
418 MachineInstr *FirstMI = MIs.back(); in expandCopyBundle()
434 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) { in expandCopyBundle()
436 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) { in expandCopyBundle()
438 std::swap(MIs[I], MIs[E - 1]); in expandCopyBundle()
449 for (MachineInstr *BundledMI : llvm::reverse(MIs)) { in expandCopyBundle()
DMachineInstr.cpp417 ArrayRef<const MachineInstr *> MIs) { in cloneMergedMemRefs() argument
419 if (MIs.empty()) { in cloneMergedMemRefs()
423 if (MIs.size() == 1) { in cloneMergedMemRefs()
424 cloneMemRefs(MF, *MIs[0]); in cloneMergedMemRefs()
430 if (MIs[0]->memoperands_empty()) { in cloneMergedMemRefs()
438 assert(&MF == MIs[0]->getMF() && in cloneMergedMemRefs()
440 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end()); in cloneMergedMemRefs()
442 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) { in cloneMergedMemRefs()
449 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands())) in cloneMergedMemRefs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc827 State.MIs.clear();
828 State.MIs.push_back(&I);
911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1080 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc783 State.MIs.clear();
784 State.MIs.push_back(&I);
888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
890 // MIs[1] Operand 1
958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
961 // MIs[1] Operand 1
975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
977 // MIs[1] Operand 1
1045 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1048 // MIs[1] Operand 1
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelector.cpp32 : Renderers(MaxRenderers), MIs() {} in MatcherState()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstr.h1606 ArrayRef<const MachineInstr *> MIs);