| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 34 class MachineInstr; variable
57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
207 bool getMemOperandWithOffset(const MachineInstr &LdSt,
222 bool isPredicated(const MachineInstr &MI) const override;
225 bool isPostIncrement(const MachineInstr &MI) const override;
229 bool PredicateInstruction(MachineInstr &MI,
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| D | HexagonVLIWPacketizer.h | 23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
79 bool ignorePseudoInstruction(const MachineInstr &MI,
84 bool isSoloInstruction(const MachineInstr &MI) override;
95 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
98 bool shouldAddToPacket(const MachineInstr &MI) override;
109 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
111 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
114 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 63 LegalizeResult legalizeInstrStep(MachineInstr &MI);
66 LegalizeResult libcall(MachineInstr &MI);
70 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
75 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
79 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
83 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
88 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
103 void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
109 void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
114 void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
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| D | CombinerHelper.h | 28 class MachineInstr; variable
36 MachineInstr *MI;
74 bool tryCombineCopy(MachineInstr &MI);
75 bool matchCombineCopy(MachineInstr &MI);
76 void applyCombineCopy(MachineInstr &MI);
80 bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
88 bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
92 bool tryCombineExtendingLoads(MachineInstr &MI);
93 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
94 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 116 bool isTriviallyReMaterializable(const MachineInstr &MI,
132 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
152 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
175 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
188 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
194 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
206 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
215 int64_t getFrameTotalSize(const MachineInstr &I) const { in getFrameTotalSize()
231 virtual int getSPAdjust(const MachineInstr &MI) const;
238 virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, in isCoalescableExtInstr()
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| D | ReachingDefAnalysis.h | 33 class MachineInstr; variable
60 DenseMap<MachineInstr *, int> InstIds;
96 int getReachingDef(MachineInstr *MI, int PhysReg);
100 MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg);
104 MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId);
107 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg);
111 bool isReachingDefLiveOut(MachineInstr *MI, int PhysReg);
115 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
120 bool isRegUsedAfter(MachineInstr *MI, int PhysReg);
123 MachineInstr *getInstWithUseBefore(MachineInstr *MI, int PhysReg);
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| D | ModuloSchedule.h | 73 class MachineInstr; variable
86 std::vector<MachineInstr *> ScheduledInstrs;
89 DenseMap<MachineInstr *, int> Cycle;
92 DenseMap<MachineInstr *, int> Stage;
106 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
107 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
108 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
133 int getStage(MachineInstr *MI) { in getStage()
139 int getCycle(MachineInstr *MI) { in getCycle()
145 ArrayRef<MachineInstr *> getInstructions() { return ScheduledInstrs; } in getInstructions()
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| D | LiveVariables.h | 89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr &MI) { in removeKill()
95 std::vector<MachineInstr *>::iterator I = find(Kills, &MI); in removeKill()
103 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
136 std::vector<MachineInstr *> PhysRegDef;
141 std::vector<MachineInstr *> PhysRegUse;
147 DenseMap<MachineInstr*, unsigned> DistanceMap;
152 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
157 void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
158 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 35 AC_EVEX_2_VEX = MachineInstr::TAsmComments
49 CondCode getCondFromBranch(const MachineInstr &MI);
52 CondCode getCondFromSETCC(const MachineInstr &MI);
55 CondCode getCondFromCMov(const MachineInstr &MI);
112 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
125 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
141 SmallVectorImpl<MachineInstr *> &CondBranches,
155 int64_t getFrameAdjustment(const MachineInstr &I) const { in getFrameAdjustment()
164 void setFrameAdjustment(MachineInstr &I, int64_t V) const { in setFrameAdjustment()
175 int getSPAdjust(const MachineInstr &MI) const override;
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| D | X86AsmPrinter.h | 83 void LowerSTACKMAP(const MachineInstr &MI);
84 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
87 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
89 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
92 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
94 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
96 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.h | 25 class MachineInstr; variable
35 typedef function_ref<bool(MachineInstr *)> IsHazardFn;
44 MachineInstr *CurrCycleInstr;
45 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
73 int checkSoftClauseHazards(MachineInstr *SMEM);
74 int checkSMRDHazards(MachineInstr *SMRD);
75 int checkVMEMHazards(MachineInstr* VMEM);
76 int checkDPPHazards(MachineInstr *DPP);
77 int checkDivFMasHazards(MachineInstr *DivFMas);
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| D | SIInstrInfo.h | 63 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
82 void swapOperands(MachineInstr &Inst) const;
84 bool moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
88 MachineInstr &Inst) const;
91 MachineInstr &Inst) const;
94 MachineInstr &Inst,
98 MachineInstr &Inst,
102 MachineInstr &Inst, unsigned Opcode) const;
104 void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
107 void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
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| D | AMDGPUInstructionSelector.h | 37 class MachineInstr; variable
55 bool select(MachineInstr &I) override;
63 const MachineInstr &GEP;
67 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } in GEPInfo()
70 bool isInstrUniform(const MachineInstr &MI) const;
78 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83 bool selectCOPY(MachineInstr &I) const;
84 bool selectPHI(MachineInstr &I) const;
85 bool selectG_TRUNC(MachineInstr &I) const;
86 bool selectG_SZA_EXT(MachineInstr &I) const;
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| D | AMDGPULegalizerInfo.h | 35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
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| D | R600InstrInfo.h | 35 class MachineInstr; variable
45 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
92 bool canBeConsideredALU(const MachineInstr &MI) const;
95 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(const MachineInstr &MI) const;
101 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(const MachineInstr &MI) const;
106 bool usesAddressRegister(MachineInstr &MI) const;
107 bool definesAddressRegister(MachineInstr &MI) const;
108 bool readsLDSSrcReg(const MachineInstr &MI) const;
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| D | AMDGPURegisterBankInfo.h | 52 MachineInstr &MI,
63 MachineInstr &MI,
66 bool executeInWaterfallLoop(MachineInstr &MI,
70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool applyMappingWideLoad(MachineInstr &MI,
76 applyMappingImage(MachineInstr &MI,
80 void lowerScalarMinMax(MachineIRBuilder &B, MachineInstr &MI) const;
88 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
89 MachineInstr &MI) const;
95 getInstrMappingForLoad(const MachineInstr &MI) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 118 SmallVectorImpl<MachineInstr *> &NewMIs) const;
122 SmallVectorImpl<MachineInstr *> &NewMIs) const;
126 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
127 unsigned ConstantOpNo, MachineInstr &DefMI,
131 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III,
132 unsigned ConstantOpNo, MachineInstr &DefMI,
139 MachineInstr *getForwardingDefMI(MachineInstr &MI,
145 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
147 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
152 const MachineInstr &DefMI,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.h | 39 getInstrMapping(const MachineInstr &MI) const override;
50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
79 SmallVector<MachineInstr *, 2> DefUses;
80 SmallVector<MachineInstr *, 2> UseDefs;
90 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
97 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
100 AmbiguousRegDefUseContainer(const MachineInstr *MI);
101 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
102 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
110 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 59 const MachineInstr &MI, unsigned DefIdx,
72 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
88 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
99 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
106 isCopyInstrImpl(const MachineInstr &MI) const override;
116 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
117 MachineInstr &MI,
147 bool isPredicated(const MachineInstr &MI) const override;
149 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
155 bool PredicateInstruction(MachineInstr &MI,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 50 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
52 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
54 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
58 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
59 const MachineInstr &MIb) const override;
61 unsigned isLoadFromStackSlot(const MachineInstr &MI,
63 unsigned isStoreToStackSlot(const MachineInstr &MI,
67 static bool isGPRZero(const MachineInstr &MI);
70 static bool isGPRCopy(const MachineInstr &MI);
73 static bool isFPRCopy(const MachineInstr &MI);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 66 MachineInstr *tryToCombine(MachineInstr &Ldst);
69 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
70 const MachineInstr *Ldst);
74 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
78 bool canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
84 MachineInstr *canJoinInstructions(MachineInstr *Ldst, MachineInstr *Add,
85 SmallVectorImpl<MachineInstr *> *Uses);
89 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
100 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 166 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
168 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
170 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
172 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
174 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
176 void expandLoadStackGuard(MachineInstr *MI) const;
198 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
206 unsigned isLoadFromStackSlot(const MachineInstr &MI,
208 unsigned isStoreToStackSlot(const MachineInstr &MI,
210 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
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| D | SystemZElimCompare.cpp | 84 Reference getRegReferences(MachineInstr &MI, unsigned Reg);
85 bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
86 SmallVectorImpl<MachineInstr *> &CCUsers);
87 bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
88 SmallVectorImpl<MachineInstr *> &CCUsers);
89 bool convertToLoadAndTest(MachineInstr &MI, MachineInstr &Compare,
90 SmallVectorImpl<MachineInstr *> &CCUsers);
91 bool convertToLogical(MachineInstr &MI, MachineInstr &Compare,
92 SmallVectorImpl<MachineInstr *> &CCUsers);
93 bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 83 static bool canHandle(const MachineInstr *MI);
88 bool canReorder(const MachineInstr *A, const MachineInstr *B);
101 Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
105 Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence) in DependenceResult()
117 DependenceResult computeDependence(const MachineInstr *MI,
118 ArrayRef<MachineInstr *> Block);
123 MachineInstr *MemOperation;
126 MachineInstr *CheckOperation;
139 MachineInstr *OnlyDependency;
142 explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation, in NullCheck()
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| D | MachineInstr.cpp | 79 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { in getMFIfAvailable()
88 static void tryToGetTargetInfo(const MachineInstr &MI, in tryToGetTargetInfo()
102 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { in addImplicitDefUseOperands()
116 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, in MachineInstr() function in MachineInstr
134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) in MachineInstr() function in MachineInstr
152 MachineRegisterInfo *MachineInstr::getRegInfo() { in getRegInfo()
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { in RemoveRegOperandsFromUseLists()
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { in AddRegOperandsToUseLists()
176 void MachineInstr::addOperand(const MachineOperand &Op) { in addOperand()
199 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { in addOperand()
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