Home
last modified time | relevance | path

Searched refs:MicroOpBufferSize (Results 1 – 25 of 48) sorted by relevance

12

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
DRetireControlUnit.cpp24 NumROBEntries(SM.MicroOpBufferSize), in RetireControlUnit()
25 AvailableEntries(SM.MicroOpBufferSize), MaxRetirePerCycle(0) { in RetireControlUnit()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCSchedule.h273 unsigned MicroOpBufferSize; member
333 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetSchedule.h161 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSISchedule.td60 // MicroOpBufferSize = 1 means that instructions will always be added
63 let MicroOpBufferSize = 1;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiSchedule.td48 let MicroOpBufferSize = 0;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td20 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
DAArch64SchedKryo.td21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
DAArch64SchedThunderX.td22 let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
DAArch64SchedA53.td19 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
DAArch64SchedCyclone.td16 let MicroOpBufferSize = 192; // Based on the reorder buffer.
DAArch64SchedExynosM3.td21 let MicroOpBufferSize = 228; // ROB size.
DAArch64SchedA57.td25 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleM4.td15 let MicroOpBufferSize = 0; // In-order
DARMScheduleR52.td22 let MicroOpBufferSize = 0; // R52 is in-order processor
DARMScheduleSwift.td42 let MicroOpBufferSize = 45; // Based on NEON renamed registers.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSchedRocket64.td15 let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
DRISCVSchedRocket32.td15 let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSchedule.td80 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
157 // MicroOpBufferSize, which should be the minimum size of either the
553 // field MicroOpBufferSize in SchedModel if the reorder buffer size is unknown.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCScheduleP9.td39 let MicroOpBufferSize = 44;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86Schedule.td694 // MicroOpBufferSize > 1 indicates that RAW dependencies can be
708 let MicroOpBufferSize = 32;
DX86ScheduleSLM.td18 let MicroOpBufferSize = 32; // Based on the reorder buffer.
DX86ScheduleZnver2.td17 // Based on the reorder buffer we define MicroOpBufferSize
18 let MicroOpBufferSize = 224;
DX86ScheduleZnver1.td17 // Based on the reorder buffer we define MicroOpBufferSize
18 let MicroOpBufferSize = 192;
DX86ScheduleAtom.td21 let MicroOpBufferSize = 0; // In-order execution, always hide latency.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsScheduleP5600.td11 int MicroOpBufferSize = 48; // min(48, 48, 64)

12