| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 74 const TargetRegisterClass *NewRC = in constrainRegClass() local
76 if (!NewRC || NewRC == OldRC) in constrainRegClass()
77 return NewRC; in constrainRegClass()
78 if (NewRC->getNumRegs() < MinNumRegs) in constrainRegClass()
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
81 return NewRC; in constrainRegClass()
125 const TargetRegisterClass *NewRC = in recomputeRegClass() local
129 if (NewRC == OldRC) in recomputeRegClass()
137 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, in recomputeRegClass()
139 if (!NewRC || NewRC == OldRC) in recomputeRegClass()
[all …]
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| D | CriticalAntiDepBreaker.cpp | 192 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
195 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
199 if (!Classes[Reg] && NewRC) in PrescanInstruction()
200 Classes[Reg] = NewRC; in PrescanInstruction()
201 else if (!NewRC || Classes[Reg] != NewRC) in PrescanInstruction()
320 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
322 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
326 if (!Classes[Reg] && NewRC) in ScanInstruction()
327 Classes[Reg] = NewRC; in ScanInstruction()
328 else if (!NewRC || Classes[Reg] != NewRC) in ScanInstruction()
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| D | RegisterCoalescer.h | 55 const TargetRegisterClass *NewRC = nullptr; variable
79 bool isPhys() const { return !NewRC; } in isPhys()
107 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| D | RegisterCoalescer.cpp | 429 NewRC = nullptr; in setRegisters()
474 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
476 if (!NewRC) in setRegisters()
481 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
485 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
488 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
492 if (!NewRC) in setRegisters()
503 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1319 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
1329 NewRC = CommonRC; in reMaterializeTrivialDef()
[all …]
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| D | TailDuplicator.cpp | 440 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
441 if (NewRC == nullptr) in duplicateInstruction()
442 NewRC = OrigRC; in duplicateInstruction()
443 Register NewReg = MRI->createVirtualRegister(NewRC); in duplicateInstruction()
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| D | PeepholeOptimizer.cpp | 761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
765 Register NewVR = MRI.createVirtualRegister(NewRC); in insertPHI()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.cpp | 281 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
283 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
287 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
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| D | AVRRegisterInfo.h | 63 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 345 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
350 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
396 if (NewRC->contains(*SI)) { in shouldCoalesce()
405 if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128)) in shouldCoalesce()
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| D | SystemZRegisterInfo.h | 92 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | CGSCCPassManager.cpp | 565 for (RefSCC *NewRC : llvm::reverse(make_range(std::next(NewRefSCCs.begin()), in updateCGAndAnalysisManagerForFunctionPass()
567 assert(NewRC != RC && "Should not encounter the current RefSCC further " in updateCGAndAnalysisManagerForFunctionPass()
569 UR.RCWorklist.insert(NewRC); in updateCGAndAnalysisManagerForFunctionPass()
571 << *NewRC << "\n"); in updateCGAndAnalysisManagerForFunctionPass()
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| D | LazyCallGraph.cpp | 1725 RefSCC *NewRC = createRefSCC(*this); in buildRefSCCs() local
1726 buildSCCs(*NewRC, Nodes); in buildRefSCCs()
1731 RefSCCIndices.insert({NewRC, PostOrderRefSCCs.size()}).second; in buildRefSCCs()
1734 PostOrderRefSCCs.push_back(NewRC); in buildRefSCCs()
1736 NewRC->verify(); in buildRefSCCs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 65 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
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| D | HexagonRegisterInfo.cpp | 243 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
250 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
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| D | HexagonVLIWPacketizer.h | 136 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| D | HexagonFrameLowering.cpp | 2094 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots() argument
2095 if (HaveRC == nullptr || HaveRC == NewRC) in optimizeSpillSlots()
2096 return NewRC; in optimizeSpillSlots()
2098 if (HaveRC->hasSubClassEq(NewRC)) in optimizeSpillSlots()
2100 if (NewRC->hasSubClassEq(HaveRC)) in optimizeSpillSlots()
2101 return NewRC; in optimizeSpillSlots()
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| D | HexagonBitSimplify.cpp | 2618 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2620 NewRC[I] = BitTracker::BitValue(C & 1); in simplifyRCmp0()
2623 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2686 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2687 NewRC[0] = BitTracker::BitValue::self(); in simplifyRCmp0()
2688 NewRC.fill(1, W, BitTracker::BitValue::Zero); in simplifyRCmp0()
2689 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
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| D | HexagonVLIWPacketizer.cpp | 354 const TargetRegisterClass *NewRC) { in isNewifiable() argument
357 if (NewRC == &Hexagon::PredRegsRegClass) { in isNewifiable()
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| D | HexagonConstPropagation.cpp | 2896 const TargetRegisterClass *NewRC; in rewriteHexConstDefs() local
2903 NewRC = &Hexagon::IntRegsRegClass; in rewriteHexConstDefs()
2905 NewRC = &Hexagon::DoubleRegsRegClass; in rewriteHexConstDefs()
2906 Register NewR = MRI->createVirtualRegister(NewRC); in rewriteHexConstDefs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 841 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
856 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); in shouldCoalesce()
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| D | ARMBaseRegisterInfo.h | 211 const TargetRegisterClass *NewRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 241 const TargetRegisterClass *NewRC,
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| D | SIRegisterInfo.cpp | 1706 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
1710 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 951 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 3846 const TargetRegisterClass *NewRC = in transformToImmFormFedByLI() local
3849 MRI.setRegClass(RegToModify, NewRC); in transformToImmFormFedByLI()
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