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Searched refs:OPERAND_REG_IMM_INT32 (Results 1 – 9 of 9) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIDefines.h127 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, enumerator
154 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
163 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,
DSIInstrInfo.h739 AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32; in isInlineConstant()
DSIRegisterInfo.td810 let OperandType = "OPERAND_REG_IMM_INT32";
DSIInstrInfo.cpp2853 case AMDGPU::OPERAND_REG_IMM_INT32: in isInlineConstant()
3259 case AMDGPU::OPERAND_REG_IMM_INT32: in verifyInstruction()
DSIInstrInfo.td941 let OperandType = "OPERAND_REG_IMM_INT32";
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp237 case AMDGPU::OPERAND_REG_IMM_INT32: in getLitEncoding()
DAMDGPUInstPrinter.cpp522 case AMDGPU::OPERAND_REG_IMM_INT32: in printOperand()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.h598 case AMDGPU::OPERAND_REG_IMM_INT32: in getOperandSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp1471 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1745 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
1785 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()