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Searched refs:OP_IMM (Results 1 – 3 of 3) sorted by relevance

/third_party/node/deps/v8/src/codegen/riscv64/
Dconstants-riscv64.h381 OP_IMM = 0b0010011, // I form: ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SARI enumerator
430 RO_ADDI = OP_IMM | (0b000 << kFunct3Shift),
431 RO_SLTI = OP_IMM | (0b010 << kFunct3Shift),
432 RO_SLTIU = OP_IMM | (0b011 << kFunct3Shift),
433 RO_XORI = OP_IMM | (0b100 << kFunct3Shift),
434 RO_ORI = OP_IMM | (0b110 << kFunct3Shift),
435 RO_ANDI = OP_IMM | (0b111 << kFunct3Shift),
436 RO_SLLI = OP_IMM | (0b001 << kFunct3Shift),
437 RO_SRLI = OP_IMM | (0b101 << kFunct3Shift),
1671 this->BaseOpcode() == OP_IMM || this->BaseOpcode() == OP_IMM_32) && in IsArithShift()
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Dconstants-riscv64.cc202 case OP_IMM: in InstructionType()
Dassembler-riscv64.cc1302 GenInstrI(funct3, OP_IMM, rd, rs1, imm12); in GenInstrALU_ri()
1308 GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt); in GenInstrShift_ri()