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Searched refs:Op1 (Results 1 – 25 of 182) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc6958 unsigned fastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1…
6961 return fastEmitInst_rr(X86::ADD8rr, &X86::GR8RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6964 unsigned fastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
6967 return fastEmitInst_rr(X86::ADD16rr, &X86::GR16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6970 unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
6973 return fastEmitInst_rr(X86::ADD32rr, &X86::GR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6976 unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
6979 return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6982 unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
6986 return fastEmitInst_rr(X86::VPADDBZ128rr, &X86::VR128XRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc1227 unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1231 … return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1234 …return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKil…
1237 return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1240 return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1245 unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1249 return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1254 unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool O…
1258 return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1263 unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc4759 unsigned fastEmit_AArch64ISD_CMEQ_MVT_v8i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1…
4763 …return fastEmitInst_rr(AArch64::CMEQv8i8, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
4768 …rch64ISD_CMEQ_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4772 …return fastEmitInst_rr(AArch64::CMEQv16i8, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKil…
4777 …rch64ISD_CMEQ_MVT_v4i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4781 …return fastEmitInst_rr(AArch64::CMEQv4i16, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill…
4786 …rch64ISD_CMEQ_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4790 …return fastEmitInst_rr(AArch64::CMEQv8i16, &AArch64::FPR128RegClass, Op0, Op0IsKill, Op1, Op1IsKil…
4795 …rch64ISD_CMEQ_MVT_v2i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
4799 …return fastEmitInst_rr(AArch64::CMEQv2i32, &AArch64::FPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill…
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/Disassembler/
DXCoreDisassembler.cpp240 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
252 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode2OpInstruction()
258 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
267 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2); in Decode3OpInstruction()
346 unsigned Op1, Op2; in Decode2RInstruction() local
347 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
351 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); in Decode2RInstruction()
359 unsigned Op1, Op2; in Decode2RImmInstruction() local
360 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
364 Inst.addOperand(MCOperand::createImm(Op1)); in Decode2RImmInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenFastISel.inc1738 unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1…
1741 return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1744 unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1747 return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1750 unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op…
1753 return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1756 unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
1760 return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
1765 unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool …
1769 return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineMulDivRem.cpp186 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul() local
187 if (match(Op1, m_AllOnes())) { in visitMul()
232 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) { in visitMul()
264 if (isa<Constant>(Op1)) { in visitMul()
269 Value *Mul = Builder.CreateMul(C1, Op1); in visitMul()
273 return BinaryOperator::CreateAdd(Builder.CreateMul(X, Op1), Mul); in visitMul()
280 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Constant(Op1C))) in visitMul()
284 if (match(Op0, m_Neg(m_Value(X))) && match(Op1, m_Neg(m_Value(Y)))) { in visitMul()
288 cast<OverflowingBinaryOperator>(Op1)->hasNoSignedWrap()) in visitMul()
301 Value *Y = Op1; in visitMul()
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DInstCombineAddSub.cpp828 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldNoWrapAdd() local
831 if (!match(Op1, m_Constant(Op1C))) in foldNoWrapAdd()
838 if (match(Op1, m_APInt(C1)) && in foldNoWrapAdd()
867 Value *Op0 = Add.getOperand(0), *Op1 = Add.getOperand(1); in foldAddWithConstant() local
869 if (!match(Op1, m_Constant(Op1C))) in foldAddWithConstant()
886 match(Op1, m_AllOnes())) in foldAddWithConstant()
892 return SelectInst::Create(X, AddOne(Op1C), Op1); in foldAddWithConstant()
896 return SelectInst::Create(X, SubOne(Op1C), Op1); in foldAddWithConstant()
903 if (!match(Op1, m_APInt(C))) in foldAddWithConstant()
915 return BinaryOperator::CreateOr(Op0, Op1); in foldAddWithConstant()
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DInstCombineShifts.cpp364 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms() local
365 assert(Op0->getType() == Op1->getType()); in commonShiftTransforms()
369 if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) { in commonShiftTransforms()
370 Value *NewExt = Builder.CreateZExt(Y, I.getType(), Op1->getName()); in commonShiftTransforms()
380 if (SelectInst *SI = dyn_cast<SelectInst>(Op1)) in commonShiftTransforms()
384 if (Constant *CUI = dyn_cast<Constant>(Op1)) in commonShiftTransforms()
396 if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C)))) in commonShiftTransforms()
406 if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) { in commonShiftTransforms()
410 Op1->getName()); in commonShiftTransforms()
682 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1, in FoldShiftByConstant() argument
[all …]
DInstCombineAndOrXor.cpp1163 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); in foldAndOfICmps() local
1166 return getNewICmpValue(Code, IsSigned, Op0, Op1, Builder); in foldAndOfICmps()
1421 Value *Op0 = BO.getOperand(0), *Op1 = BO.getOperand(1), *X; in reassociateFCmps() local
1423 if (match(Op1, m_FCmp(Pred, m_Value(), m_AnyZeroFP()))) in reassociateFCmps()
1424 std::swap(Op0, Op1); in reassociateFCmps()
1431 !match(Op1, m_BinOp(BO1)) || BO1->getOpcode() != Opcode) in reassociateFCmps()
1539 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in foldCastedBitwiseLogic() local
1554 CastInst *Cast1 = dyn_cast<CastInst>(Op1); in foldCastedBitwiseLogic()
1605 Value *Op1 = I.getOperand(1); in foldAndToXor() local
1619 if (Op0->hasOneUse() || Op1->hasOneUse()) in foldAndToXor()
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DInstCombineCompares.cpp1446 Value *Op0 = Cmp.getOperand(0), *Op1 = Cmp.getOperand(1); in foldICmpWithConstant() local
1449 if (Pred == ICmpInst::ICMP_UGT && match(Op1, m_ConstantInt(CI)) && in foldICmpWithConstant()
2732 Value *Op1 = Cmp.getOperand(1); in foldICmpBitCast() local
2747 match(Op1, m_Zero())) in foldICmpBitCast()
2751 if (Pred == ICmpInst::ICMP_SLT && match(Op1, m_One())) in foldICmpBitCast()
2755 if (Pred == ICmpInst::ICMP_SGT && match(Op1, m_AllOnes())) in foldICmpBitCast()
2764 if (Cmp.isEquality() && match(Op1, m_Zero())) in foldICmpBitCast()
2771 (isa<Constant>(Op1) || isa<BitCastInst>(Op1))) { in foldICmpBitCast()
2774 if (auto *BC2 = dyn_cast<BitCastInst>(Op1)) in foldICmpBitCast()
2775 Op1 = BC2->getOperand(0); in foldICmpBitCast()
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DInstructionCombining.cpp341 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(I.getOperand(1)); in SimplifyAssociativeOrCommutative() local
378 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeOrCommutative()
380 Value *B = Op1->getOperand(0); in SimplifyAssociativeOrCommutative()
381 Value *C = Op1->getOperand(1); in SimplifyAssociativeOrCommutative()
426 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeOrCommutative()
428 Value *B = Op1->getOperand(0); in SimplifyAssociativeOrCommutative()
429 Value *C = Op1->getOperand(1); in SimplifyAssociativeOrCommutative()
449 if (Op0 && Op1 && in SimplifyAssociativeOrCommutative()
450 Op0->getOpcode() == Opcode && Op1->getOpcode() == Opcode && in SimplifyAssociativeOrCommutative()
452 match(Op1, m_OneUse(m_BinOp(m_Value(B), m_Constant(C2))))) { in SimplifyAssociativeOrCommutative()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DInstructionSimplify.cpp267 if (BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS)) in ExpandBinOp() local
268 if (Op1->getOpcode() == OpcodeToExpand) { in ExpandBinOp()
270 Value *A = LHS, *B = Op1->getOperand(0), *C = Op1->getOperand(1); in ExpandBinOp()
305 BinaryOperator *Op1 = dyn_cast<BinaryOperator>(RHS); in SimplifyAssociativeBinOp() local
327 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
329 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
330 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
369 if (Op1 && Op1->getOpcode() == Opcode) { in SimplifyAssociativeBinOp()
371 Value *B = Op1->getOperand(0); in SimplifyAssociativeBinOp()
372 Value *C = Op1->getOperand(1); in SimplifyAssociativeBinOp()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenFastISel.inc2788 unsigned fastEmit_ARMISD_CMP_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool…
2792 return fastEmitInst_rr(ARM::t2CMPrr, &ARM::GPRnopcRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2795 return fastEmitInst_rr(ARM::tCMPr, &ARM::tGPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2798 return fastEmitInst_rr(ARM::CMPrr, &ARM::GPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2803 unsigned fastEmit_ARMISD_CMP_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool…
2805 case MVT::i32: return fastEmit_ARMISD_CMP_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2812 unsigned fastEmit_ARMISD_CMPFP_MVT_f16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bo…
2816 return fastEmitInst_rr(ARM::VCMPH, &ARM::HPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
2821 unsigned fastEmit_ARMISD_CMPFP_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bo…
2825 return fastEmitInst_rr(ARM::VCMPS, &ARM::SPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp345 const MachineOperand &Op1 = MI->getOperand(1); in profit() local
347 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0; in profit()
703 MachineOperand &Op1 = MI->getOperand(1); in splitImmediate() local
704 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
705 uint64_t V = Op1.getImm(); in splitImmediate()
730 MachineOperand &Op1 = MI->getOperand(1); in splitCombine() local
740 if (!Op1.isReg()) { in splitCombine()
742 .add(Op1); in splitCombine()
745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
760 MachineOperand &Op1 = MI->getOperand(1); in splitExt() local
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/pnacl-llvm/include/llvm/Bitcode/NaCl/
DNaClBitCodes.h237 static inline bool operator<(const NaClBitCodeAbbrevOp &Op1,
239 return Op1.Compare(Op2) < 0;
242 static inline bool operator<=(const NaClBitCodeAbbrevOp &Op1,
244 return Op1.Compare(Op2) <= 0;
247 static inline bool operator==(const NaClBitCodeAbbrevOp &Op1,
249 return Op1.Compare(Op2) == 0;
252 static inline bool operator!=(const NaClBitCodeAbbrevOp &Op1,
254 return Op1.Compare(Op2) != 0;
257 static inline bool operator>=(const NaClBitCodeAbbrevOp &Op1,
259 return Op1.Compare(Op2) >= 0;
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDFAPacketizer.cpp282 bool VLIWPacketizerList::alias(const MachineMemOperand &Op1, in alias() argument
285 if (!Op1.getValue() || !Op2.getValue()) in alias()
288 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
289 int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset; in alias()
293 AA->alias(MemoryLocation(Op1.getValue(), Overlapa, in alias()
294 UseTBAA ? Op1.getAAInfo() : AAMDNodes()), in alias()
307 for (const MachineMemOperand *Op1 : MI1.memoperands()) in alias() local
309 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.cpp135 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
138 Ops[2].getAsInteger(10, Op1); in parseGenericRegister()
142 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
150 uint32_t Op1 = (Bits >> 11) & 0x7; in genericRegisterString() local
155 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp189 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue() local
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
199 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18); in getRiMemoryOpValue()
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue() local
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
226 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15); in getRrMemoryOpValue()
260 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getSplsOpValue() local
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
270 Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12); in getSplsOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DBypassSlowDivision.cpp89 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
203 Value *Op1 = I->getOperand(1); in isHashLikeValue() local
204 ConstantInt *C = dyn_cast<ConstantInt>(Op1); in isHashLikeValue()
205 if (!C && isa<BitCastInst>(Op1)) in isHashLikeValue()
206 C = dyn_cast<ConstantInt>(cast<BitCastInst>(Op1)->getOperand(0)); in isHashLikeValue()
328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
329 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
333 if (Op1 && Op2) in insertOperandRuntimeCheck()
334 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
336 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCBranchCoalescing.cpp336 const MachineOperand &Op1 = OpList1[i]; in identicalOperands() local
339 LLVM_DEBUG(dbgs() << "Op1: " << Op1 << "\n" in identicalOperands()
342 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
344 if (Op1.isReg() && in identicalOperands()
345 Register::isPhysicalRegister(Op1.getReg()) in identicalOperands()
348 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) { in identicalOperands()
359 if (Op1.isReg() && Op2.isReg() && in identicalOperands()
360 Register::isVirtualRegister(Op1.getReg()) && in identicalOperands()
362 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); in identicalOperands()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DSelectionDAGTargetInfo.h52 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemcpy() argument
68 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, in EmitTargetCodeForMemmove() argument
81 SDValue Chain, SDValue Op1, in EmitTargetCodeForMemset() argument
94 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
131 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
171 if (Op1.getType() != Op2.getType()) in isSameOperand()
174 switch (Op1.getType()) { in isSameOperand()
176 return Op1.getReg() == Op2.getReg(); in isSameOperand()
178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
293 MachineOperand &Op1 = AluIter->getOperand(1); in isSuitableAluInstr() local
298 if (!isSameOperand(Dest, Base) || !isSameOperand(Dest, Op1)) in isSuitableAluInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIOptimizeExecMaskingPreRA.cpp231 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair() local
233 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
234 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
235 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
238 Register SelReg = Op1->getReg(); in optimizeVcndVcmpPair()
239 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS); in optimizeVcndVcmpPair()
247 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
250 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
251 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
32 SDValue Chain, SDValue Op1, SDValue Op2,
37 SDValue Chain, SDValue Op1, SDValue Op2,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/AggressiveInstCombine/
DAggressiveInstCombine.cpp177 Value *Op0, *Op1; in matchAndOrChain() local
186 if (match(V, m_And(m_Value(Op0), m_Value(Op1)))) in matchAndOrChain()
187 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); in matchAndOrChain()
190 if (match(V, m_Or(m_Value(Op0), m_Value(Op1)))) in matchAndOrChain()
191 return matchAndOrChain(Op0, MOps) && matchAndOrChain(Op1, MOps); in matchAndOrChain()
285 Value *Op1 = I.getOperand(1); in tryToRecognizePopCount() local
289 match(Op1, m_SpecificInt(MaskShift))) { in tryToRecognizePopCount()

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