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Searched refs:OpNode (Results 1 – 25 of 36) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1805 SDPatternOperator OpNode>
1808 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1866 SDNode OpNode>
1868 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1871 SDNode OpNode>
1873 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1879 SDNode OpNode, SDNode OpNode_setflags> {
1880 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1884 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1903 SDPatternOperator OpNode,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrAVX512.td1268 X86VectorVTInfo _, SDPatternOperator OpNode,
1274 (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX,
1279 X86VectorVTInfo _, SDPatternOperator OpNode,
1289 def : Pat <(_.VT (OpNode SrcRC:$src)),
1293 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1297 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1303 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1307 OpNode, SrcRC, Subreg>, EVEX_V512;
1310 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1312 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
[all …]
DX86InstrFMA.td179 SDPatternOperator OpNode,
185 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
200 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
214 (OpNode RC:$src2, (load addr:$src3), RC:$src1))]>,
220 SDPatternOperator OpNode, X86FoldableSchedWrite sched> {
236 (OpNode (load addr:$src3), RC:$src1, RC:$src2))]>,
244 SDNode OpNode, RegisterClass RC,
247 x86memop, RC, OpNode, sched>;
249 x86memop, RC, OpNode, sched>;
[all …]
DX86InstrFPStack.td177 multiclass FPBinary_rr<SDNode OpNode> {
181 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
183 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
185 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
190 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
197 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
199 (OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
204 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
206 (OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
211 (OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
[all …]
DX86InstrXOP.td94 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
106 (vt128 (OpNode (vt128 VR128:$src1),
113 (vt128 (OpNode (vt128 (load addr:$src1)),
140 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
244 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128,
253 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
261 (vt128 (OpNode (vt128 VR128:$src1),
[all …]
DX86InstrSSE.td20 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
44 SDPatternOperator OpNode, RegisterClass RC,
53 [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>,
60 [(set RC:$dst, (VT (OpNode RC:$src1, mem_cpat:$src2)))], d>,
66 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
76 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>,
83 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
190 multiclass sse12_move_rr<SDNode OpNode, ValueType vt,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td166 multiclass I3<string OpcStr, SDNode OpNode> {
170 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
178 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
182 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
[all …]
DMipsInstrFPU.td109 SDPatternOperator OpNode= null_frag> :
112 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
118 SDPatternOperator OpNode = null_frag> {
119 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
120 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
126 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
134 SDPatternOperator OpNode = null_frag> :
137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
143 SDPatternOperator OpNode= null_frag> {
[all …]
DMipsMSAInstrInfo.td1122 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1129 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1133 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1140 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1144 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1151 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1155 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1162 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1166 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1173 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[all …]
DMicroMipsDSPInstrInfo.td179 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
185 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
215 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
221 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
252 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
257 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
284 class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
291 class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
336 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
341 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
DMicroMipsInstrFPU.td14 SDPatternOperator OpNode = null_frag> {
15 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
20 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
111 SDPatternOperator OpNode = null_frag> {
112 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
116 def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
DMipsInstrInfo.td1315 SDPatternOperator OpNode = null_frag>:
1318 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1328 SDPatternOperator OpNode = null_frag> :
1331 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
1357 SDPatternOperator OpNode = null_frag,
1361 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
1366 SDPatternOperator OpNode = null_frag>:
1369 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
1382 SDPatternOperator OpNode = null_frag,
1386 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
[all …]
DMipsCondMov.td36 SDPatternOperator OpNode = null_frag> :
39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
46 SDPatternOperator OpNode = null_frag> :
49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
DMicroMipsInstrInfo.td209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
291 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
295 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
303 SDPatternOperator OpNode = null_frag> :
306 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
317 SDPatternOperator OpNode = null_frag> :
320 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
[all …]
DMips16InstrInfo.td1303 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1304 Mips16Pat<(OpNode CPU16Regs:$r),
1310 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1311 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1323 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1333 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1334 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1341 class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1342 Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
[all …]
DMicroMips32r6InstrInfo.td608 SDPatternOperator OpNode=null_frag>
613 list<dag> Pattern = [(set GPROpnd:$rd, (OpNode GPROpnd:$rs, GPROpnd:$rt))];
669 InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
728 SDPatternOperator OpNode = null_frag> : MipsR6Inst {
732 list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
856 SDPatternOperator OpNode = null_frag> : HARDFLOAT {
860 list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
883 SDPatternOperator OpNode = null_frag>
888 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
[all …]
/third_party/skia/src/gpu/
DGrAuditTrail.cpp47 OpNode* opNode = new OpNode(proxyID); in addOp()
59 OpNode& consumerOp = *fOpsTask[index]; in opsCombined()
66 OpNode& consumedOp = *fOpsTask[consumedIndex]; in opsCombined()
89 const OpNode* bn = fOpsTask[opsTaskID].get(); in copyOutFromOpsTask()
196 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const { in toJson()
209 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const {} in toJson()
DGrAuditTrail.h141 struct OpNode { struct
142 OpNode(const GrSurfaceProxy::UniqueID& proxyID) : fProxyUniqueID(proxyID) { } in OpNode() argument
149 typedef SkTArray<std::unique_ptr<OpNode>, true> OpsTask; argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
411 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
437 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
438 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
621 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td272 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
287 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
289 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt, [], []>;
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
298 multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
300 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
308 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
479 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td2519 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2522 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2525 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2528 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2584 ValueType TyD, ValueType TyQ, SDNode OpNode>
2587 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2602 ValueType TyQ, ValueType TyD, SDNode OpNode>
2605 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2631 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2635 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td213 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
216 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
219 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
230 SDNode OpNode> {
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
236 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
239 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
242 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
251 SDNode OpNode> {
254 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.td308 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
314 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
319 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
337 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
342 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
347 [(set Ty:$dst, (OpNode ADDRri:$addr))],
353 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
361 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
363 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
364 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
[all …]

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