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Searched refs:OrigMI (Results 1 – 7 of 7) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNDPPCombine.cpp74 MachineInstr *createDPPInst(MachineInstr &OrigMI,
80 MachineInstr *createDPPInst(MachineInstr &OrigMI,
157 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, in createDPPInst() argument
163 auto OrigOp = OrigMI.getOpcode(); in createDPPInst()
170 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, in createDPPInst()
171 OrigMI.getDebugLoc(), TII->get(DPPOp)); in createDPPInst()
174 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
195 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
218 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveRangeEdit.cpp106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, in allUsesAvailableAt() argument
111 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) { in allUsesAvailableAt()
112 const MachineOperand &MO = OrigMI->getOperand(i); in allUsesAvailableAt()
150 assert(RM.OrigMI && "No defining instruction for remattable value"); in canRematerializeAt()
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
154 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) in canRematerializeAt()
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
170 assert(RM.OrigMI && "Invalid remat"); in rematerializeAt()
171 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri); in rematerializeAt()
DInlineSpiller.cpp571 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in reMaterializeFor()
589 if (RM.OrigMI->canFoldAsLoad() && in reMaterializeFor()
590 foldMemoryOperand(Ops, RM.OrigMI)) { in reMaterializeFor()
DModuloSchedule.cpp1160 MachineInstr *OrigMI = OrigInstr->second; in rewriteScheduledInstr() local
1161 int StageSched = Schedule.getStage(OrigMI); in rewriteScheduledInstr()
1162 int CycleSched = Schedule.getCycle(OrigMI); in rewriteScheduledInstr()
1170 (CyclePhi <= CycleSched || OrigMI->isPHI())) in rewriteScheduledInstr()
DSplitKit.cpp648 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); in defFromParent()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp85 bool getSuperRegDestIfDead(MachineInstr *OrigMI,
188 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, in getSuperRegDestIfDead() argument
192 Register OrigDestReg = OrigMI->getOperand(0).getReg(); in getSuperRegDestIfDead()
251 unsigned Opc = OrigMI->getOpcode(); (void)Opc; in getSuperRegDestIfDead()
260 for (auto &MO: OrigMI->implicit_operands()) { in getSuperRegDestIfDead()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveRangeEdit.h101 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
203 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains member