Searched refs:OrigOp (Results 1 – 6 of 6) sorted by relevance
163 auto OrigOp = OrigMI.getOpcode(); in createDPPInst() local164 auto DPPOp = getDPPOp(OrigOp); in createDPPInst()460 auto OrigOp = OrigMI.getOpcode(); in combineDPPMov() local461 if (OrigOp == AMDGPU::REG_SEQUENCE) { in combineDPPMov()490 if (TII->isVOP3(OrigOp)) { in combineDPPMov()491 if (!TII->hasVALU32BitEncoding(OrigOp)) { in combineDPPMov()504 } else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) { in combineDPPMov()
496 SDValue OrigOp = N->getOperand(i); in AnalyzeNewNode() local497 SDValue Op = OrigOp; in AnalyzeNewNode()507 } else if (Op != OrigOp) { in AnalyzeNewNode()
1332 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]); in VerifyAndAdjustOperands() local1336 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg())) in VerifyAndAdjustOperands()1342 if (!OrigOp.isMem()) in VerifyAndAdjustOperands()1346 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands()1353 return Error(OrigOp.getStartLoc(), in VerifyAndAdjustOperands()1374 OrigOp.getStartLoc(), in VerifyAndAdjustOperands()1379 FinalOp.Mem.Size = OrigOp.Mem.Size; in VerifyAndAdjustOperands()1380 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg; in VerifyAndAdjustOperands()
535 Value *OrigOp) { in materializeStack() argument549 RenameIter == RenameStack.begin() ? OrigOp : (RenameIter - 1)->Def; in materializeStack()
615 SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
2767 auto *OrigOp = &*Op; in makePossiblePHIOfOps() local2772 if (Op != OrigOp && Op != I) in makePossiblePHIOfOps()2781 (Op != OrigOp || OpIsSafeForPHIOfOps(Op, PHIBlock, VisitedOps)); in makePossiblePHIOfOps()