Searched refs:PrefReg (Results 1 – 4 of 4) sorted by relevance
762 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument766 RegAllocHints[VReg].second.push_back(PrefReg); in setRegAllocationHint()771 void addRegAllocationHint(unsigned VReg, unsigned PrefReg) { in addRegAllocationHint() argument773 RegAllocHints[VReg].second.push_back(PrefReg); in addRegAllocationHint()778 void setSimpleHint(unsigned VReg, unsigned PrefReg) { in setSimpleHint() argument779 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
82 PrefReg, ///< Block entry/exit prefers a register. enumerator
142 case PrefReg: in addBias()
1199 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()1202 ? SpillPlacement::PrefReg in addSplitConstraints()1623 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); in calcGlobalSplitCost()1625 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); in calcGlobalSplitCost()