| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrSPE.td | 19 bits<5> RB;
25 let Inst{16-20} = RB;
32 let RB = 0;
46 bits<5> RB;
51 let Inst{16-20} = RB;
60 bits<5> RB;
66 let Inst{16-20} = RB;
73 let RB = 0;
87 bits<5> RB;
94 let Inst{16-20} = RB;
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| D | PPCInstrHTM.td | 106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
107 (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
113 (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
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| D | PPCInstrFormats.td | 546 bits<5> RB;
552 let Inst{16-20} = RB;
562 bits<5> RB;
567 let Inst{16-20} = RB;
596 bits<5> RB;
599 let Inst{16-20} = RB;
723 // [PO RT /// RB XO RC]
927 // [PO RT RA RB XO /]
934 bits<5> RB;
942 let Inst{16-20} = RB;
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.h | 115 bool alias(RegisterRef RA, RegisterRef RB) const { in alias()
117 return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); in alias()
118 return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); in alias()
152 bool aliasRR(RegisterRef RA, RegisterRef RB) const;
166 static bool isCoverOf(RegisterRef RA, RegisterRef RB, in isCoverOf()
168 return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); in isCoverOf()
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| D | RDFRegisters.cpp | 131 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { in aliasRR()
133 assert(Register::isPhysicalRegister(RB.Reg)); in aliasRR()
136 MCRegUnitMaskIterator UMB(RB.Reg, &TRI); in aliasRR()
147 if (PB.second.any() && (PB.second & RB.Mask).none()) { in aliasRR()
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| D | HexagonVLIWPacketizer.cpp | 251 MachineBasicBlock::iterator RB = Begin; in runOnMachineFunction() local
252 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF)) in runOnMachineFunction()
253 ++RB; in runOnMachineFunction()
256 MachineBasicBlock::iterator RE = RB; in runOnMachineFunction()
263 if (RB != End) in runOnMachineFunction()
264 Packetizer.PacketizeMIs(&MB, RB, RE); in runOnMachineFunction()
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| D | HexagonGenInsert.cpp | 236 BitValueOrdering(const RegisterOrdering &RB) : BaseOrd(RB) {} in BitValueOrdering()
530 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
627 void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB, in buildOrderingBT() argument
631 BitValueOrdering BVO(RB); in buildOrderingBT()
637 for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I) in buildOrderingBT()
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| D | HexagonEarlyIfConv.cpp | 473 const MachineOperand &RB = MI.getOperand(3); in computePhiCost() local
474 assert(RA.isReg() && RB.isReg()); in computePhiCost()
476 if (RA.getSubReg() != 0 || RB.getSubReg() != 0) { in computePhiCost()
481 const MachineInstr *Def3 = MRI->getVRegDef(RB.getReg()); in computePhiCost()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEInfo.cpp | 302 GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { in addNodeIDRegType()
303 ID.AddPointer(RB); in addNodeIDRegType()
347 auto *RB = MRI.getRegBankOrNull(Reg); in addNodeIDMachineOperand() local
348 if (RB) in addNodeIDMachineOperand()
349 addNodeIDRegType(RB); in addNodeIDMachineOperand()
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| D | RegisterBankInfo.cpp | 93 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank() local
94 return RB; in getRegBank()
140 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister() local
142 if (RB && !RB->covers(RC)) in constrainGenericRegister()
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| /third_party/node/deps/ngtcp2/nghttp3/lib/ |
| D | nghttp3_ringbuf.h | 106 #define nghttp3_ringbuf_len(RB) ((RB)->len) argument
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| /third_party/node/deps/ngtcp2/ngtcp2/lib/ |
| D | ngtcp2_ringbuf.h | 112 #define ngtcp2_ringbuf_len(RB) ((RB)->len) argument
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| /third_party/python/Lib/test/ |
| D | tokenize_tests.txt | 117 x = rb'abc' + rB'ABC' + Rb'ABC' + RB'ABC'
118 y = rb"abc" + rB"ABC" + Rb"ABC" + RB"ABC"
120 x = rb'\\' + RB'\\'
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterBank.inc | 97 for (const auto &RB : RegBanks)
98 assert(Index++ == RB->getID() && "Index != ID");
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterBank.inc | 108 for (const auto &RB : RegBanks)
109 assert(Index++ == RB->getID() && "Index != ID");
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 1766 const RegisterBank &RB, in getRegClassForSizeOnBank() argument
1770 switch (RB.getID()) { in getRegClassForSizeOnBank()
1783 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass : in getRegClassForSizeOnBank()
1786 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass : in getRegClassForSizeOnBank()
1789 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_96RegClass : in getRegClassForSizeOnBank()
1792 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass : in getRegClassForSizeOnBank()
1795 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass : in getRegClassForSizeOnBank()
1798 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_256RegClass : in getRegClassForSizeOnBank()
1801 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_512RegClass : in getRegClassForSizeOnBank()
1804 return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_1024RegClass : in getRegClassForSizeOnBank()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 112 const RegisterBank &RB,
332 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() argument
335 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
345 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
363 getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits, in getMinClassForRegBank() argument
365 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
1011 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch() local
1012 if (RB.getID() != AArch64::GPRRegBankID) in selectCompareBranch()
1442 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select() local
1443 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
[all …]
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| D | AArch64RegisterBankInfo.h | 64 unsigned ValLength, const RegisterBank &RB);
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| D | AArch64GenRegisterBankInfo.def | 122 const RegisterBank &RB) {
125 Map.RegBank == &RB;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 73 unsigned getLoadStoreOp(const LLT &Ty, const RegisterBank &RB, unsigned Opc,
127 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass()
170 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
180 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
395 const RegisterBank &RB, in getLoadStoreOp() argument
404 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
407 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
410 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
412 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterBank.inc | 133 for (const auto &RB : RegBanks)
134 assert(Index++ == RB->getID() && "Index != ID");
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterBank.inc | 151 for (const auto &RB : RegBanks)
152 assert(Index++ == RB->getID() && "Index != ID");
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| /third_party/parse5/packages/parse5/lib/common/ |
| D | html.ts | 134 RB = 'rb', enumerator
306 RB, enumerator
456 [TAG_NAMES.RB, TAG_ID.RB],
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| /third_party/skia/gm/ |
| D | image.cpp | 121 RB = W * 4 + 8, enumerator
125 fBufferSize = RB * H; in ImageGM()
166 sk_sp<SkSurface> surf0(SkSurface::MakeRasterDirect(info, fBuffer, RB)); in onDraw()
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| /third_party/openssl/doc/man3/ |
| D | SSL_rstate_string.pod | 41 =item "RB"/"read body"
|