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Searched refs:RC_MASK_XYZW (Results 1 – 18 of 18) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_pair_regalloc.c344 writemask = RC_MASK_XYZW; in variable_get_class()
466 return reg / RC_MASK_XYZW; in reg_get_index()
471 return (reg % RC_MASK_XYZW) + 1; in reg_get_writemask()
480 return (index * RC_MASK_XYZW) + (writemask - 1); in get_reg_id()
502 for(a_mask = 1; a_mask <= RC_MASK_XYZW; a_mask++) { in add_register_conflicts()
503 for (b_mask = a_mask + 1; b_mask <= RC_MASK_XYZW; in add_register_conflicts()
696 s->regs = ra_alloc_reg_set(NULL, R500_PFS_NUM_TEMP_REGS * RC_MASK_XYZW, in rc_init_regalloc_state()
Dradeon_emulate_branches.c168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
190 inst_cmp->U.I.SrcReg[0].Negate = RC_MASK_XYZW; in inject_cmp()
298 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in fix_output_writes()
Dradeon_opcodes.c495 srcmasks[0] |= RC_MASK_XYZW; in rc_compute_sources_for_writemask()
523 srcmasks[0] |= RC_MASK_XYZW; in rc_compute_sources_for_writemask()
524 srcmasks[1] |= RC_MASK_XYZW; in rc_compute_sources_for_writemask()
Dradeon_program.c160 RC_MASK_XYZW); in rc_find_free_temporary()
176 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in rc_alloc_instruction()
Dradeon_program_alu.c160 newreg.Negate = newreg.Negate ^ RC_MASK_XYZW; in negate()
334 if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) { in transform_LIT()
343 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in transform_LIT()
684 dst.WriteMask = RC_MASK_XYZW; in transform_r300_vertex_fix_LIT()
757 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_SGT()
758 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_SGT()
766 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_SLE()
767 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in transform_r300_vertex_SLE()
1127 inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW; in radeonTransformDeriv()
Dradeon_program_tex.c172 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in radeonTransformTEX()
229 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW; in radeonTransformTEX()
231 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW; in radeonTransformTEX()
441 (!c->is_r500 && inst->U.I.DstReg.WriteMask != RC_MASK_XYZW))) { in radeonTransformTEX()
453 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in radeonTransformTEX()
Dr3xx_vertprog.c57 return mask & RC_MASK_XYZW; in t_dst_mask()
172 src->Negate ? RC_MASK_XYZW : RC_MASK_NONE) | in t_src_scalar()
258 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) | in ei_lit()
265 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) | in ei_lit()
272 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) | in ei_lit()
721 new_inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in transform_nonnative_modifiers()
795 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in rc_vs_add_artificial_outputs()
Dradeon_optimize.c117 sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW; in src_clobbered_reads_cb()
121 sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW; in src_clobbered_reads_cb()
245 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mad()
259 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW; in constant_folding_mad()
280 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mul()
293 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mul()
Dradeon_rename_regs.c82 RC_MASK_XYZW); in rc_rename_regs()
Dradeon_program_print.c164 if (dst.WriteMask != RC_MASK_XYZW) { in rc_print_dst_register()
235 int trivial_negate = (src.Negate == RC_MASK_NONE || src.Negate == RC_MASK_XYZW); in rc_print_src_register()
237 if (src.Negate == RC_MASK_XYZW) in rc_print_src_register()
Dradeon_program_constants.h159 #define RC_MASK_XYZW (RC_MASK_X|RC_MASK_Y|RC_MASK_Z|RC_MASK_W) macro
Dradeon_dataflow_swizzles.c75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW; in rewrite_source()
Dradeon_dataflow_deadcode.c187 refmask &= RC_MASK_XYZW; in update_instruction()
Dradeon_compiler_util.c46 mask &= RC_MASK_XYZW; in rc_swizzle_to_writemask()
Dradeon_compiler.c327 inst_add->U.I.SrcReg[1].Negate = RC_MASK_XYZW; in rc_transform_fragment_face()
Dradeon_dataflow.c51 refmask &= RC_MASK_XYZW; in reads_normal_callback()
/third_party/mesa3d/src/gallium/drivers/r300/compiler/tests/
Drc_test_helpers.c166 src_reg->Negate = RC_MASK_XYZW; in init_rc_normal_src()
312 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in init_rc_normal_dst()
/third_party/mesa3d/src/gallium/drivers/r300/
Dr300_tgsi_to_rc.c188 dst->Negate = src->Register.Negate ? RC_MASK_XYZW : 0; in transform_srcreg()