| /third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 17 glm_uvec4 Reg2; in glm_i128_interleave() local
26 Reg2 = _mm_slli_si128(Reg1, 2); in glm_i128_interleave()
27 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
32 Reg2 = _mm_slli_si128(Reg1, 1); in glm_i128_interleave()
33 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
38 Reg2 = _mm_slli_epi32(Reg1, 4); in glm_i128_interleave()
39 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
44 Reg2 = _mm_slli_epi32(Reg1, 2); in glm_i128_interleave()
45 Reg1 = _mm_or_si128(Reg2, Reg1); in glm_i128_interleave()
50 Reg2 = _mm_slli_epi32(Reg1, 1); in glm_i128_interleave()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 640 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
651 Reg2 = getXRegFromWReg(Reg2); in generateCompactUnwindEncoding()
653 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && in generateCompactUnwindEncoding()
656 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && in generateCompactUnwindEncoding()
659 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && in generateCompactUnwindEncoding()
662 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && in generateCompactUnwindEncoding()
665 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && in generateCompactUnwindEncoding()
670 Reg2 = getDRegFromBReg(Reg2); in generateCompactUnwindEncoding()
676 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && in generateCompactUnwindEncoding()
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
1877 if (Reg2 == AArch64::FP) in invalidateWindowsRegisterPairing()
1881 if (Reg2 == Reg1 + 1) in invalidateWindowsRegisterPairing()
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
1893 return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI); in invalidateRegisterPairing()
1898 return Reg2 == AArch64::LR; in invalidateRegisterPairing()
1907 unsigned Reg2 = AArch64::NoRegister; member
1914 bool isPaired() const { return Reg2 != AArch64::NoRegister; } in isPaired()
1988 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
1993 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 420 bool &HaveReg2, Register &Reg2,
836 bool &HaveReg2, Register &Reg2, in parseAddress() argument
865 if (parseRegister(Reg2)) in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
904 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) in parseAddress()
939 if (parseAddressRegister(Reg2)) in parseAddress()
941 Base = Regs[Reg2.Num]; in parseAddress()
952 if (parseAddressRegister(Reg2)) in parseAddress()
954 Base = Regs[Reg2.Num]; in parseAddress()
976 if (parseAddressRegister(Reg2)) in parseAddress()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 94 unsigned Reg1, unsigned Reg2);
97 unsigned Reg1, unsigned Reg2, unsigned Reg3);
100 unsigned Reg1, unsigned Reg2, unsigned FPReg1,
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| D | MipsAsmPrinter.cpp | 876 unsigned Reg2) { in EmitInstrRegReg() argument
885 Reg1 = Reg2; in EmitInstrRegReg()
886 Reg2 = Temp; in EmitInstrRegReg()
890 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegReg()
896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg() argument
900 I.addOperand(MCOperand::createReg(Reg2)); in EmitInstrRegRegReg()
907 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair() argument
911 Reg1 = Reg2; in EmitMovFPIntPair()
912 Reg2 = temp; in EmitMovFPIntPair()
915 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2); in EmitMovFPIntPair()
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| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
388 if (Registers[i + 1] == Reg2) in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
481 if (Reg1 != Reg2) in ReduceXWtoXWP()
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| D | Mips16InstrInfo.cpp | 278 unsigned Reg1, unsigned Reg2) const { in adjustStackPtrBig()
289 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); in adjustStackPtrBig()
293 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
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| D | MipsTargetStreamer.h | 131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
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| D | Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 188 unsigned Reg2,
403 unsigned Reg2, in getOperandGatherWeight() argument
417 if (Def->modifiesRegister(Reg2, TRI)) in getOperandGatherWeight()
541 unsigned Reg2 = OperandMasks[J].Reg; in collectCandidates() local
550 " and " << printReg(Reg2, SubReg2) << '\n'); in collectCandidates()
552 unsigned Weight = getOperandGatherWeight(MI, Reg1, Reg2, StallCycles); in collectCandidates()
558 unsigned FreeBanks2 = getFreeBanks(Reg2, SubReg2, Mask2, UsedBanks); in collectCandidates()
563 Candidates.push(Candidate(&MI, Reg2, FreeBanks2, Weight in collectCandidates()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
193 && Reg2 != OldFMAReg) { in processBlock()
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| D | PPCVSXSwapRemoval.cpp | 873 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
874 MI->getOperand(1).setReg(Reg2); in handleSpecialSwappables()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg() argument
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 98 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
102 !Register::isPhysicalRegister(Reg2)) in contains()
104 return MC->contains(Reg1, Reg2); in contains()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 176 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
191 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl()
199 Reg0 = Reg2; in commuteInstructionImpl()
201 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
222 CommutedMI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
235 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl()
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| D | AggressiveAntiDepBreaker.h | 105 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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| D | AggressiveAntiDepBreaker.cpp | 94 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
100 unsigned Group2 = GetGroup(Reg2); in UnionGroups()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1386 StringRef Reg2(R2); in processInstruction() local
1387 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1401 StringRef Reg2(R2); in processInstruction() local
1402 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1417 StringRef Reg2(R2); in processInstruction() local
1418 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1749 StringRef Reg2(R2); in processInstruction() local
1753 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
1893 StringRef Reg2(R2); in processInstruction() local
1897 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2))); in processInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 750 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
753 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
755 if (Reg0 != Reg2) { in ReduceTo2Addr()
785 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
786 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
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| D | A15SDOptimizer.cpp | 83 unsigned Reg2);
449 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) { in createRegSequence() argument
457 .addReg(Reg2) in createRegSequence()
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| D | ARMFastISel.cpp | 2797 unsigned Reg2 = 0; in SelectShift() local
2799 Reg2 = getRegForValue(Src2Value); in SelectShift()
2800 if (Reg2 == 0) return false; in SelectShift()
2813 MIB.addReg(Reg2); in SelectShift()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 218 unsigned Reg2, SMLoc IDLoc, in emitRRR() argument
220 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
224 unsigned Reg2, MCOperand Op3, SMLoc IDLoc, in emitRRRX() argument
230 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
78 return contains(Reg1) && contains(Reg2); in contains()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCDwarf.cpp | 1336 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
1339 Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); in EmitCFIInstruction()
1343 Streamer.EmitULEB128IntValue(Reg2); in EmitCFIInstruction()
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