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Searched refs:RegNum (Results 1 – 25 of 55) sorted by relevance

123

/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceRegistersMIPS32.h68 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
69 assert(int(Reg_GPR_First) <= int(RegNum)); in getEncodedGPR()
70 assert(unsigned(RegNum) <= Reg_GPR_Last); in getEncodedGPR()
71 return GPRRegister(RegNum - Reg_GPR_First); in getEncodedGPR()
74 static inline bool isGPRReg(RegNumT RegNum) { in isGPRReg() argument
75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) && in isGPRReg()
76 (unsigned(RegNum) <= Reg_GPR_Last)) || in isGPRReg()
77 ((int(Reg_I64PAIR_First) <= int(RegNum)) && in isGPRReg()
78 (unsigned(RegNum) <= Reg_I64PAIR_Last)); in isGPRReg()
82 static inline FPRRegister getEncodedFPR(RegNumT RegNum) { in getEncodedFPR() argument
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DIceRegistersARM32.h105 static inline void assertValidRegNum(RegNumT RegNum) { in assertValidRegNum() argument
106 (void)RegNum; in assertValidRegNum()
107 assert(RegNum.hasValue()); in assertValidRegNum()
110 static inline bool isGPRegister(RegNumT RegNum) { in isGPRegister() argument
111 RegNum.assertIsValid(); in isGPRegister()
112 return RegTable[RegNum].IsGPR; in isGPRegister()
125 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
126 RegNum.assertIsValid(); in getEncodedGPR()
127 return GPRRegister(RegTable[RegNum].Encoding); in getEncodedGPR()
140 static inline bool isGPR(RegNumT RegNum) { in isGPR() argument
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DIceRegistersX8664.h80 static inline const char *getRegName(RegNumT RegNum) { in getRegName() argument
89 RegNum.assertIsValid(); in getRegName()
90 return RegNames[RegNum]; in getRegName()
93 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
102 RegNum.assertIsValid(); in getEncodedGPR()
103 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
104 return GPRRegs[RegNum]; in getEncodedGPR()
107 static inline ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg() argument
116 RegNum.assertIsValid(); in getEncodedByteReg()
117 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
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DIceRegistersX8632.h95 static inline const char *getRegName(RegNumT RegNum) { in getRegName() argument
104 RegNum.assertIsValid(); in getRegName()
105 return RegNames[RegNum]; in getRegName()
108 static inline GPRRegister getEncodedGPR(RegNumT RegNum) { in getEncodedGPR() argument
117 RegNum.assertIsValid(); in getEncodedGPR()
118 assert(GPRRegs[RegNum] != GPRRegister::Encoded_Not_GPR); in getEncodedGPR()
119 return GPRRegs[RegNum]; in getEncodedGPR()
122 static inline ByteRegister getEncodedByteReg(RegNumT RegNum) { in getEncodedByteReg() argument
131 RegNum.assertIsValid(); in getEncodedByteReg()
132 assert(ByteRegs[RegNum] != ByteRegister::Encoded_Not_ByteReg); in getEncodedByteReg()
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DIceRegAlloc.cpp434 const RegNumT RegNum = *RegNumBVIter(Iter.RegMask).begin(); in addSpillFill() local
435 Iter.Cur->setRegNumTmp(RegNum); in addSpillFill()
436 Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType()); in addSpillFill()
621 const auto RegNum = Cur->getRegNum(); in allocatePrecoloredRegister() local
623 assert(Cur->getRegNumTmp() == RegNum); in allocatePrecoloredRegister()
626 const auto &Aliases = *RegAliases[RegNum]; in allocatePrecoloredRegister()
648 const RegNumT RegNum = in allocateFreeRegister() local
650 Iter.Cur->setRegNumTmp(RegNum); in allocateFreeRegister()
655 const auto &Aliases = *RegAliases[RegNum]; in allocateFreeRegister()
741 const auto RegNum = Item->getRegNumTmp(); in handleNoFreeRegisters() local
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DIceTargetLoweringX8664.h148 Variable *getPhysicalRegister(RegNumT RegNum,
150 const char *getRegName(RegNumT RegNum, Type Ty) const override;
253 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
392 RegNumT RegNum = RegNumT());
393 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
402 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
417 Variable *copyToReg8(Operand *Src, RegNumT RegNum = RegNumT());
418 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT());
422 Variable *makeZeroedRegister(Type Ty, RegNumT RegNum = RegNumT());
426 Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
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DIceTargetLoweringX8632.h147 Variable *getPhysicalRegister(RegNumT RegNum,
149 const char *getRegName(RegNumT RegNum, Type Ty) const override;
257 Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
396 RegNumT RegNum = RegNumT());
397 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
406 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
421 Variable *copyToReg8(Operand *Src, RegNumT RegNum = RegNumT());
422 Variable *copyToReg(Operand *Src, RegNumT RegNum = RegNumT());
426 Variable *makeZeroedRegister(Type Ty, RegNumT RegNum = RegNumT());
430 Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
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DIceTargetLoweringMIPS32.h67 Variable *getPhysicalRegister(RegNumT RegNum,
69 const char *getRegName(RegNumT RegNum, Type Ty) const override;
634 RegNumT RegNum = RegNumT());
636 Variable *legalizeToVar(Operand *From, RegNumT RegNum = RegNumT());
638 Variable *legalizeToReg(Operand *From, RegNumT RegNum = RegNumT());
640 Variable *makeReg(Type Ty, RegNumT RegNum = RegNumT());
648 Variable *I32Reg(RegNumT RegNum = RegNumT()) {
649 return makeReg(IceType_i32, RegNum);
652 Variable *F32Reg(RegNumT RegNum = RegNumT()) {
653 return makeReg(IceType_f32, RegNum);
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DIceTargetLoweringX8664.cpp778 Variable *TargetX8664::getPhysicalRegister(RegNumT RegNum, Type Ty) { in getPhysicalRegister() argument
783 assert(unsigned(RegNum) < PhysicalRegisters[Ty].size()); in getPhysicalRegister()
784 Variable *Reg = PhysicalRegisters[Ty][RegNum]; in getPhysicalRegister()
787 Reg->setRegNum(RegNum); in getPhysicalRegister()
788 PhysicalRegisters[Ty][RegNum] = Reg; in getPhysicalRegister()
796 assert(RegX8664::getGprForType(Ty, RegNum) == RegNum); in getPhysicalRegister()
800 const char *TargetX8664::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
801 return RegX8664::getRegName(RegX8664::getGprForType(Ty, RegNum)); in getRegName()
934 for (RegNumT RegNum : RegNumBVIter(Pushed)) { in addProlog() local
935 assert(RegNum == RegX8664::getBaseReg(RegNum)); in addProlog()
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DIceOperand.cpp211 V->RegNum = NewRegNum.hasValue() ? NewRegNum : RegNum; in asType()
228 const auto RegNum = getRegNum(); in getRematerializableOffset() local
229 if (RegNum == Target->getFrameReg()) { in getRematerializableOffset()
231 } else if (RegNum != Target->getStackReg()) { in getRematerializableOffset()
579 Str << Func->getTarget()->getRegName(RegNum, getType()); in dump()
DIceTargetLoweringX8632.cpp768 Variable *TargetX8632::getPhysicalRegister(RegNumT RegNum, Type Ty) { in getPhysicalRegister() argument
773 assert(unsigned(RegNum) < PhysicalRegisters[Ty].size()); in getPhysicalRegister()
774 Variable *Reg = PhysicalRegisters[Ty][RegNum]; in getPhysicalRegister()
777 Reg->setRegNum(RegNum); in getPhysicalRegister()
778 PhysicalRegisters[Ty][RegNum] = Reg; in getPhysicalRegister()
786 assert(RegX8632::getGprForType(Ty, RegNum) == RegNum); in getPhysicalRegister()
790 const char *TargetX8632::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
791 return RegX8632::getRegName(RegX8632::getGprForType(Ty, RegNum)); in getRegName()
922 for (RegNumT RegNum : RegNumBVIter(Pushed)) { in addProlog() local
923 assert(RegNum == RegX8632::getBaseReg(RegNum)); in addProlog()
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DIceTargetLoweringMIPS32.cpp236 RegNumT RegNum; in getCallStackArgumentsSizeBytes() local
237 if (CC.argInReg(Ty, i, &RegNum)) { in getCallStackArgumentsSizeBytes()
1016 const char *RegMIPS32::getRegName(RegNumT RegNum) { in getRegName() argument
1017 RegNum.assertIsValid(); in getRegName()
1018 return RegNames[RegNum]; in getRegName()
1021 const char *TargetMIPS32::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
1023 return RegMIPS32::getRegName(RegNum); in getRegName()
1026 Variable *TargetMIPS32::getPhysicalRegister(RegNumT RegNum, Type Ty) { in getPhysicalRegister() argument
1031 RegNum.assertIsValid(); in getPhysicalRegister()
1032 Variable *Reg = PhysicalRegisters[Ty][RegNum]; in getPhysicalRegister()
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DIceTargetLoweringARM32.cpp331 const auto RegNum = RegNumT::fromInt(i); in staticInit() local
333 GPRArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
335 I64ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
337 FP32ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
339 FP64ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
341 Vec128ArgInitializer[Entry.CCArg - 1] = RegNum; in staticInit()
367 [](RegNumT RegNum) -> std::string { in staticInit() argument
370 std::string Name = RegARM32::getRegName(RegNum); in staticInit()
1027 const char *TargetARM32::getRegName(RegNumT RegNum, Type Ty) const { in getRegName() argument
1029 return RegARM32::getRegName(RegNum); in getRegName()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const { in getDwarfRegNum() argument
74 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
76 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
81 Optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum, in getLLVMRegNum() argument
88 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
90 if (I != M + Size && I->FromReg == RegNum) in getLLVMRegNum()
95 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const { in getDwarfRegNumFromDwarfEHRegNum()
104 if (Optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) in getDwarfRegNumFromDwarfEHRegNum()
106 return RegNum; in getDwarfRegNumFromDwarfEHRegNum()
109 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const { in getSEHRegNum()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
48 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
68 int RegsLeft = NumArgRegs - RegNum; in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
72 if (RegNum != NumArgRegs && RegsLeft < 4) { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
93 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/AsmParser/
DAVRAsmParser.cpp205 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
207 return std::make_unique<AVROperand>(RegNum, S, E); in CreateReg()
216 CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) { in CreateMemri() argument
217 return std::make_unique<AVROperand>(RegNum, Val, S, E); in CreateMemri()
337 int RegNum = matchFn(Name); in parseRegisterName() local
343 if (RegNum == AVR::NoRegister) { in parseRegisterName()
344 RegNum = matchFn(Name.lower()); in parseRegisterName()
346 if (RegNum == AVR::NoRegister) { in parseRegisterName()
347 RegNum = matchFn(Name.upper()); in parseRegisterName()
350 return RegNum; in parseRegisterName()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/
DAVRInstPrinter.cpp89 const char *AVRInstPrinter::getPrettyRegisterName(unsigned RegNum, in getPrettyRegisterName() argument
94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); in getPrettyRegisterName()
95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
98 return getRegisterName(RegNum); in getPrettyRegisterName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp205 unsigned RegNum; member
252 return Reg.RegNum; in getReg()
429 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
431 Op->Reg.RegNum = RegNum; in CreateReg()
1767 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1768 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2 in processInstruction()
1770 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1); in processInstruction()
1775 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum); in processInstruction()
1784 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction() local
1785 if (RegNum & 1) { // Odd mapped to raw:hi in processInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/AsmParser/
DMSP430AsmParser.cpp197 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() argument
199 return std::make_unique<MSP430Operand>(k_Reg, RegNum, S, E); in CreateReg()
207 static std::unique_ptr<MSP430Operand> CreateMem(unsigned RegNum, in CreateMem() argument
210 return std::make_unique<MSP430Operand>(RegNum, Val, S, E); in CreateMem()
213 static std::unique_ptr<MSP430Operand> CreateIndReg(unsigned RegNum, SMLoc S, in CreateIndReg() argument
215 return std::make_unique<MSP430Operand>(k_IndReg, RegNum, S, E); in CreateIndReg()
218 static std::unique_ptr<MSP430Operand> CreatePostIndReg(unsigned RegNum, SMLoc S, in CreatePostIndReg() argument
220 return std::make_unique<MSP430Operand>(k_PostIndReg, RegNum, S, E); in CreatePostIndReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp311 unsigned RegNum; member
337 unsigned RegNum; member
541 return Reg.RegNum; in getReg()
551 return VectorList.RegNum; in getVectorListStart()
1037 Reg.RegNum); in isNeonVectorRegLo()
1112 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
1117 AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(Reg.RegNum); in isGPR64as32()
1123 Reg.RegNum); in isWSeqPair()
1129 Reg.RegNum); in isXSeqPair()
1814 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/
DLanaiAsmParser.cpp69 bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override;
121 unsigned RegNum; member
156 return Reg.RegNum; in getReg()
592 static std::unique_ptr<LanaiOperand> createReg(unsigned RegNum, SMLoc Start, in createReg()
595 Op->Reg.RegNum = RegNum; in createReg()
694 unsigned RegNum; in parseRegister() local
699 RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); in parseRegister()
700 if (RegNum == 0) in parseRegister()
703 return LanaiOperand::createReg(RegNum, Start, End); in parseRegister()
708 bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, in ParseRegister() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h506 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
510 Optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
514 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
518 int getSEHRegNum(MCRegister RegNum) const;
522 int getCodeViewRegNum(MCRegister RegNum) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h829 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
831 OutMIs[InsnID].addDef(RegNum, RegState::Implicit); in executeMatchTable()
834 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
840 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
842 OutMIs[InsnID].addUse(RegNum, RegState::Implicit); in executeMatchTable()
845 << InsnID << "], " << RegNum << ")\n"); in executeMatchTable()
851 int64_t RegNum = MatchTable[CurrentIdx++]; in executeMatchTable() local
854 OutMIs[InsnID].addReg(RegNum, RegFlags); in executeMatchTable()
858 << InsnID << "], " << RegNum << ", " << RegFlags << ")\n"); in executeMatchTable()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DStackMaps.cpp93 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum() local
94 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
95 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
97 assert(RegNum >= 0 && "Invalid Dwarf register number."); in getDwarfRegNum()
98 return (unsigned)RegNum; in getDwarfRegNum()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp231 unsigned RegNum; member
287 return Reg.RegNum; in getReg()
387 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
390 Op->Reg.RegNum = RegNum; in CreateReg()
420 Op.Reg.RegNum = IntPairRegs[regIdx / 2]; in MorphToIntPairReg()
431 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
454 Op.Reg.RegNum = Reg; in MorphToQuadReg()
467 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2]; in MorphToCoprocPairReg()

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