Searched refs:RegSet (Results 1 – 11 of 11) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 69 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
255 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
258 if (RegSet.count(*AI)) in isRegInSet()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 274 using RegSet = SparseSet<IndexMaskPair>; variable
275 RegSet Regs;
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 75 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
343 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
348 if (RegSet.count(*AI)) in IsRegInSet()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 108 using RegSet = DenseSet<unsigned>; typedef
117 RegSet regsLive;
141 RegSet regsKilled;
145 RegSet regsLiveOut;
149 RegSet vregsPassed;
153 RegSet vregsRequired;
171 bool addPassed(const RegSet &RS) { in addPassed()
173 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) in addPassed()
190 bool addRequired(const RegSet &RS) { in addRequired()
192 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) in addRequired()
[all …]
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| D | RegAllocPBQP.cpp | 150 using RegSet = std::set<unsigned>; typedef in __anon0102e8e70111::RegAllocPBQP
154 RegSet VRegsToAlloc, EmptyIntervalVRegs;
748 for (RegSet::const_iterator in finalizeAlloc()
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| D | AggressiveAntiDepBreaker.cpp | 266 SmallSet<unsigned, 4> RegSet; in AntiDepEdges() local
270 if (RegSet.insert(P->getReg()).second) in AntiDepEdges()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 133 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
448 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
451 if (RegSet.test(*AI)) in isRegInSet()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 37 const uint8_t *const RegSet; variable
73 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 209 void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
551 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet, in updateLiveness() argument
554 for (unsigned R : RegSet) { in updateLiveness()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLowering.cpp | 197 std::vector<SmallBitVector> &RegSet) { in filterTypeToRegisterSet() argument
211 RegSet[TypeIndex][RegIndex] = TypeToRegisterSet[TypeIndex][RegIndex]; in filterTypeToRegisterSet()
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| D | IceTargetLowering.h | 282 enum RegSet { enum
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