| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 93 static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII, in isSendMsgTraceDataOrGDS()
125 static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr) { in getHWReg()
137 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()
141 if ((SIInstrInfo::isVMEM(*MI) || in getHazardType()
142 SIInstrInfo::isFLAT(*MI)) in getHazardType()
155 if (SIInstrInfo::isVALU(*MI) && checkVALUHazards(MI) > 0) in getHazardType()
158 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0) in getHazardType()
185 if (SIInstrInfo::isMAI(*MI) && checkMAIHazards(MI) > 0) in getHazardType()
200 static void insertNoopInBundle(MachineInstr *MI, const SIInstrInfo &TII) { in insertNoopInBundle()
251 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoopsCommon()
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| D | SIModeRegister.cpp | 144 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
146 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
148 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
150 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
153 const SIInstrInfo *TII, Status InstrMode);
171 const SIInstrInfo *TII) { in getInstructionMode()
193 const SIInstrInfo *TII, Status InstrMode) { in insertSetreg()
228 const SIInstrInfo *TII) { in processBlockPhase1()
327 const SIInstrInfo *TII) { in processBlockPhase2()
363 const SIInstrInfo *TII) { in processBlockPhase3()
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| D | SIInstrInfo.cpp | 86 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST) in SIInstrInfo() function in SIInstrInfo
130 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
146 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr()
261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
436 bool SIInstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1, in shouldClusterMemOps()
504 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, in shouldScheduleLoadsNear()
516 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB, in reportIllegalCopy()
531 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, in copyPhysReg()
740 int SIInstrInfo::commuteOpcode(unsigned Opcode) const { in commuteOpcode()
758 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB, in materializeImmediate()
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| D | AMDGPUMCInstLower.cpp | 83 case SIInstrInfo::MO_GOTPCREL: in getVariantKind()
85 case SIInstrInfo::MO_GOTPCREL32_LO: in getVariantKind()
87 case SIInstrInfo::MO_GOTPCREL32_HI: in getVariantKind()
89 case SIInstrInfo::MO_REL32_LO: in getVariantKind()
91 case SIInstrInfo::MO_REL32_HI: in getVariantKind()
93 case SIInstrInfo::MO_ABS32_LO: in getVariantKind()
95 case SIInstrInfo::MO_ABS32_HI: in getVariantKind()
119 if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD) in getLongBranchBlockExpr()
122 assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD); in getLongBranchBlockExpr()
178 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo()); in lower()
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| D | SIFrameLowering.h | 16 class SIInstrInfo; variable
64 const SIInstrInfo *TII,
70 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
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| D | SIShrinkInstructions.cpp | 71 static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates()
128 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKImmOperand()
134 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) { in isKUImmOperand()
140 static bool isKImmOrKUImmOperand(const SIInstrInfo *TII, in isKImmOrKUImmOperand()
158 static bool isReverseInlineImm(const SIInstrInfo *TII, in isReverseInlineImm()
182 static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) { in shrinkScalarCompare()
228 const SIInstrInfo *TII = ST.getInstrInfo(); in shrinkMIMG()
317 const SIInstrInfo *TII, in shrinkScalarLogicOp()
456 const SIInstrInfo *TII) { in matchSwap()
555 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIPeepholeSDWA.cpp | 75 const SIInstrInfo *TII;
121 virtual MachineInstr *potentialToConvert(const SIInstrInfo *TII) = 0;
122 virtual bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) = 0;
154 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
155 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
162 uint64_t getSrcMods(const SIInstrInfo *TII,
181 MachineInstr *potentialToConvert(const SIInstrInfo *TII) override;
182 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
202 bool convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) override;
330 uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII, in getSrcMods()
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| D | AMDGPUMacroFusion.cpp | 32 const SIInstrInfo &TII = static_cast<const SIInstrInfo&>(TII_); in shouldScheduleAdjacent()
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| D | SIOptimizeExecMasking.cpp | 181 static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) { in removeTerminatorBit()
224 const SIInstrInfo &TII, in fixTerminators()
239 const SIInstrInfo &TII, in findExecCopy()
274 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIFormMemoryClauses.cpp | 101 return SIInstrInfo::isFLAT(MI) || SIInstrInfo::isVMEM(MI); in isVMEMClauseInst()
105 return SIInstrInfo::isSMRD(MI); in isSMEMClauseInst()
313 const SIInstrInfo *TII = ST->getInstrInfo(); in runOnMachineFunction()
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| D | GCNHazardRecognizer.h | 29 class SIInstrInfo; variable
48 const SIInstrInfo &TII;
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| D | SIFrameLowering.cpp | 94 const SIInstrInfo *TII, unsigned SpillReg, in buildPrologSpill()
142 const SIInstrInfo *TII, unsigned SpillReg, in buildEpilogReload()
190 const SIInstrInfo *TII = ST.getInstrInfo(); in emitFlatScratchInit()
271 const SIInstrInfo *TII, in getReservedPrivateSegmentBufferReg()
320 const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI, in getReservedPrivateSegmentWaveByteOffsetReg()
405 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionPrologue()
538 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEntryFunctionScratchSetup()
687 const SIInstrInfo *TII = ST.getInstrInfo(); in emitPrologue()
829 const SIInstrInfo *TII = ST.getInstrInfo(); in emitEpilogue()
1100 const SIInstrInfo *TII = ST.getInstrInfo(); in eliminateCallFramePseudoInstr()
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| D | SIOptimizeExecMaskingPreRA.cpp | 39 const SIInstrInfo *TII;
109 const SIInstrInfo &TII, in getOrNonExecReg()
122 const SIInstrInfo &TII, in getOrExecSource()
194 const SIInstrInfo *TII = ST.getInstrInfo(); in optimizeVcndVcmpPair()
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| D | AMDGPURegisterBankInfo.h | 30 class SIInstrInfo; variable
46 const SIInstrInfo *TII;
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| D | SIRegisterInfo.cpp | 314 assert(SIInstrInfo::isMUBUF(*MI)); in getMUBUFInstrOffset()
323 if (!SIInstrInfo::isMUBUF(*MI)) in getFrameIndexInstrOffset()
353 const SIInstrInfo *TII = ST.getInstrInfo(); in materializeFrameBaseRegister()
379 const SIInstrInfo *TII = ST.getInstrInfo(); in resolveFrameIndex()
416 if (!SIInstrInfo::isMUBUF(*MI)) in isFrameOffsetLegal()
552 const SIInstrInfo *TII = ST.getInstrInfo(); in spillVGPRtoAGPR()
579 const SIInstrInfo *TII = ST.getInstrInfo(); in buildMUBUFOffsetLoadStore()
626 const SIInstrInfo *TII = ST.getInstrInfo(); in buildSpillLoadStore()
760 const SIInstrInfo *TII = ST.getInstrInfo(); in spillSGPR()
871 const SIInstrInfo *TII = ST.getInstrInfo(); in restoreSGPR()
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| D | SIFoldOperands.cpp | 89 const SIInstrInfo *TII;
134 static bool isInlineConstantIfFolded(const SIInstrInfo *TII, in isInlineConstantIfFolded()
171 static bool frameIndexMayFold(const SIInstrInfo *TII, in frameIndexMayFold()
185 const SIInstrInfo &TII, in updateOperand()
331 const SIInstrInfo *TII) { in tryAddToFoldList()
460 static bool isUseSafeToFold(const SIInstrInfo *TII, in isUseSafeToFold()
473 const SIInstrInfo *TII, const MachineRegisterInfo &MRI) { in getRegSeqInit()
503 static bool tryToFoldACImm(const SIInstrInfo *TII, in tryToFoldACImm()
988 const SIInstrInfo *TII, in tryConstantFoldOp()
1101 static bool tryFoldInst(const SIInstrInfo *TII, in tryFoldInst()
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| D | AMDGPUInstructionSelector.h | 42 class SIInstrInfo; variable
193 const SIInstrInfo &TII;
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| D | SIFixupVectorISel.cpp | 159 const SIInstrInfo *TII, in fixupGlobalSaddr()
225 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIFixVGPRCopies.cpp | 51 const SIInstrInfo *TII = ST.getInstrInfo(); in runOnMachineFunction()
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| D | SIInsertWaitcnts.cpp | 265 RegInterval getRegInterval(const MachineInstr *MI, const SIInstrInfo *TII,
280 void updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI,
348 void setExpScore(const MachineInstr *MI, const SIInstrInfo *TII,
371 const SIInstrInfo *TII = nullptr;
464 const SIInstrInfo *TII, in getRegInterval()
506 const SIInstrInfo *TII, in setExpScore()
520 void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, in updateByEvent()
1248 } else if (SIInstrInfo::isVMEM(Inst) && in updateEventWaitcntAfter()
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| D | AMDGPUSubtarget.cpp | 758 const SIInstrInfo *TII;
760 MemOpClusterMutation(const SIInstrInfo *tii) : TII(tii) {} in MemOpClusterMutation()
805 const SIInstrInfo *TII;
809 FillMFMAShadowMutation(const SIInstrInfo *tii) : TII(tii) {} in FillMFMAShadowMutation()
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| D | SIFixSGPRCopies.cpp | 119 const SIInstrInfo *TII;
204 const SIInstrInfo *TII) { in tryChangeVGPRtoSGPRinCopy()
242 const SIInstrInfo *TII, in foldVGPRCopyIntoRegSequence()
325 const SIInstrInfo *TII, in isSafeToFoldImmIntoCopy()
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| D | SILowerControlFlow.cpp | 81 const SIInstrInfo *TII = nullptr;
148 const SIInstrInfo *TII) { in isSimpleIf()
367 && SIInstrInfo::isVALU(*Def); in emitIfBreak()
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| D | SIMachineFunctionInfo.h | 875 const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
884 const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
893 const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
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| D | SISchedule.td | 14 const SIInstrInfo *TII =
15 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
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