| /third_party/ltp/tools/sparse/sparse-src/validation/optim/ |
| D | canonical-cmpe-minmax.c | 2 #define SMIN (-__INT_MAX__-1) macro
7 int lt_smin(int a) { return (a < (SMIN + 1)) == (a == SMIN); } in lt_smin()
8 int ge_smin(int a) { return (a >= (SMIN + 1)) == (a != SMIN); } in ge_smin()
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| D | canonical-cmps-minmax.c | 2 #define SMIN (-__INT_MAX__-1) macro
7 int le_smin(int a) { return (a <= SMIN) == (a == SMIN); } in le_smin()
8 int gt_smin(int a) { return (a > SMIN) == (a != SMIN); } in gt_smin()
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| D | cmps-minmax.c | 2 #define SMIN (-__INT_MAX__-1) macro
4 int lt_smin(int a) { return (a < SMIN) + 1; } in lt_smin()
7 int ge_smin(int a) { return (a >= SMIN) + 0; } in ge_smin()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2767 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
2783 {ISD::SMIN, MVT::v2i64, 6}, in getMinMaxReductionCost()
2785 {ISD::SMIN, MVT::v4i32, 6}, in getMinMaxReductionCost()
2787 {ISD::SMIN, MVT::v8i16, 4}, in getMinMaxReductionCost()
2789 {ISD::SMIN, MVT::v16i8, 8}, in getMinMaxReductionCost()
2795 {ISD::SMIN, MVT::v2i64, 9}, in getMinMaxReductionCost()
2797 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" in getMinMaxReductionCost()
2799 {ISD::SMIN, MVT::v8i16, 2}, in getMinMaxReductionCost()
2801 {ISD::SMIN, MVT::v16i8, 3}, in getMinMaxReductionCost()
2806 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" in getMinMaxReductionCost()
[all …]
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| D | X86ISelLowering.cpp | 904 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom); in X86TargetLowering()
1087 setOperationAction(ISD::SMIN, MVT::v16i8, Legal); in X86TargetLowering()
1088 setOperationAction(ISD::SMIN, MVT::v4i32, Legal); in X86TargetLowering()
1286 setOperationAction(ISD::SMIN, MVT::v4i64, Custom); in X86TargetLowering()
1302 setOperationAction(ISD::SMIN, VT, HasInt256 ? Legal : Custom); in X86TargetLowering()
1561 setOperationAction(ISD::SMIN, VT, Legal); in X86TargetLowering()
1673 setOperationAction(ISD::SMIN, VT, Legal); in X86TargetLowering()
1818 setOperationAction(ISD::SMIN, VT, Legal); in X86TargetLowering()
25858 Opcode = (Opcode == ISD::UMIN ? ISD::SMIN : ISD::SMAX); in LowerMINMAX()
25866 case ISD::SMIN: CC = ISD::CondCode::SETLT; break; in LowerMINMAX()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 445 SMIN, SMAX, UMIN, UMAX, enumerator
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| D | TargetLowering.h | 2239 case ISD::SMIN: in isCommutativeBinOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 266 case ISD::SMIN: return "smin"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 81 case ISD::SMIN: in PromoteIntegerResult()
740 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax); in PromoteIntRes_ADDSUBSAT()
1881 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break; in ExpandIntegerResult()
2212 case ISD::SMIN: in getExpandedMinMaxOps()
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| D | LegalizeVectorTypes.cpp | 120 case ISD::SMIN: in ScalarizeVectorResult()
931 case ISD::SMIN: in SplitVectorResult()
2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; in SplitVecOp_VECREDUCE()
2723 case ISD::SMIN: in WidenVectorResult()
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| D | SelectionDAG.cpp | 3364 case ISD::SMIN: in computeKnownBits()
3371 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
3697 case ISD::SMIN: in ComputeNumSignBits()
3704 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
4802 case ISD::SMIN: return C1.sle(C2) ? C1 : C2; in FoldValue()
5199 case ISD::SMIN: in getNode()
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| D | LegalizeVectorOps.cpp | 442 case ISD::SMIN: in LegalizeOp()
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| D | LegalizeDAG.cpp | 3167 case ISD::SMIN: in ExpandNode()
3176 case ISD::SMIN: Pred = ISD::SETLT; break; in ExpandNode()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 98 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 449 setOperationAction(ISD::SMIN, MVT::i16, Legal); in SITargetLowering()
620 setOperationAction(ISD::SMIN, MVT::v2i16, Legal); in SITargetLowering()
647 setOperationAction(ISD::SMIN, MVT::v4i16, Custom); in SITargetLowering()
727 setTargetDAGCombine(ISD::SMIN); in SITargetLowering()
4095 case ISD::SMIN: in LowerOperation()
9030 case ISD::SMIN: in minMaxOpcToMin3Max3Opc()
9186 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
9317 case ISD::SMIN: in performExtractVectorEltCombine()
10008 case ISD::SMIN: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 346 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
2671 B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B, in LowerFP_TO_FP16()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 346 setOperationAction(ISD::SMIN, Ty, Legal); in addMSAIntType()
2034 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2046 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 646 setOperationAction(ISD::SMIN, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 385 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 2624 // FastEmit functions for ISD::SMIN.
3299 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 193 setOperationAction(ISD::SMIN, VT, Legal); in AArch64TargetLowering()
928 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2972 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
12947 ReplaceReductionResults(N, Results, DAG, ISD::SMIN, AArch64ISD::SMINV); in ReplaceNodeResults()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenFastISel.inc | 2124 // FastEmit functions for ISD::SMIN.
3422 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 497 setOperationAction(ISD::SMIN, Ty, Legal); in NVPTXTargetLowering()
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| /third_party/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4953 ### SMIN ### subsection
10067 ### SMIN ### subsection
10077 ### SMIN ### subsection
|