| /third_party/ffmpeg/libavutil/x86/ |
| D | cpu.h | 36 #define X86_SSE3(flags) CPUEXT(flags, SSE3)
37 #define X86_SSE3_FAST(flags) CPUEXT_FAST(flags, SSE3)
38 #define X86_SSE3_SLOW(flags) CPUEXT_SLOW(flags, SSE3)
62 #define EXTERNAL_SSE3(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE3)
63 #define EXTERNAL_SSE3_FAST(flags) CPUEXT_SUFFIX_FAST(flags, _EXTERNAL, SSE3)
64 #define EXTERNAL_SSE3_SLOW(flags) CPUEXT_SUFFIX_SLOW(flags, _EXTERNAL, SSE3)
93 #define INLINE_SSE3(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE3)
94 #define INLINE_SSE3_FAST(flags) CPUEXT_SUFFIX_FAST(flags, _INLINE, SSE3)
95 #define INLINE_SSE3_SLOW(flags) CPUEXT_SUFFIX_SLOW(flags, _INLINE, SSE3)
|
| D | tx_float_init.c | 67 TX_DEF(fft2, FFT, 2, 2, 2, 0, 128, NULL, sse3, SSE3, AV_TX_INPLACE, 0),
68 … TX_DEF(fft2, FFT, 2, 2, 2, 0, 192, b8_i0, sse3, SSE3, AV_TX_INPLACE | FF_TX_PRESHUFFLE, 0),
72 TX_DEF(fft8, FFT, 8, 8, 2, 0, 128, b8_i0, sse3, SSE3, AV_TX_INPLACE, 0),
73 … TX_DEF(fft8_ns, FFT, 8, 8, 2, 0, 192, b8_i0, sse3, SSE3, AV_TX_INPLACE | FF_TX_PRESHUFFLE, 0),
|
| /third_party/skia/src/core/ |
| D | SkCpu.h | 17 SSE3 = 1 << 2, enumerator
71 features |= SSE3; in Supports()
97 features &= (SSE1 | SSE2 | SSE3 | SSSE3 | SSE41 | SSE42 | AVX); in Supports()
99 features &= (SSE1 | SSE2 | SSE3 | SSSE3 | SSE41); in Supports()
|
| D | SkCpu.cpp | 45 if (abcd[2] & (1<< 0)) { features |= SkCpu:: SSE3; } in read_cpu_features()
|
| /third_party/skia/third_party/externals/swiftshader/src/Common/ |
| D | CPUID.hpp | 58 static bool SSE3; member in sw::CPUID
113 return SSE3 && enableSSE3; in supportsSSE3()
|
| D | CPUID.cpp | 36 bool CPUID::SSE3 = detectSSE3(); member in sw::CPUID
213 return SSE3 = (registers[2] & 0x00000001) != 0; in detectSSE3()
|
| /third_party/node/deps/v8/src/codegen/ |
| D | cpu-features.h | 20 SSE3, enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86Subtarget.h | 64 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
586 bool hasSSE3() const { return X86SSELevel >= SSE3; } in hasSSE3()
|
| D | X86.td | 68 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
69 "Enable SSE3 instructions",
441 // SSE3) with better latency/throughput than the alternative sequence.
1011 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
|
| D | X86InstrFormats.td | 657 // SSE3 Instruction Templates:
659 // S3I - SSE3 instructions with PD prefixes.
660 // S3SI - SSE3 instructions with XS prefix.
661 // S3DI - SSE3 instructions with XD prefix.
|
| D | X86InstrFPStack.td | 571 // FISTTP requires SSE3 even though it's a FPStack op.
|
| D | X86InstrSSE.td | 4326 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4392 // SSE3 - Replicate Double FP - MOVDDUP
4447 // SSE3 - Move Unaligned Integer
4467 // SSE3 - Arithmetic
4519 // SSE3 Instructions
|
| /third_party/node/deps/v8/src/codegen/ia32/ |
| D | assembler-ia32.cc | 144 if (cpu.has_sse3()) SetSupported(SSE3); in ProbeImpl()
165 if (!FLAG_enable_sse3) SetUnsupported(SSE3); in ProbeImpl()
166 if (!FLAG_enable_ssse3 || !IsSupported(SSE3)) SetUnsupported(SSSE3); in ProbeImpl()
186 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSSE3), in PrintFeatures()
334 EnableCpuFeature(SSE3); in Assembler()
1899 DCHECK(IsEnabled(SSE3)); in fisttp_s()
1906 DCHECK(IsEnabled(SSE3)); in fisttp_d()
2250 DCHECK(IsEnabled(SSE3)); in haddps()
2368 DCHECK(IsEnabled(SSE3)); in movddup()
2377 DCHECK(IsEnabled(SSE3)); in movshdup()
|
| /third_party/node/deps/v8/src/codegen/x64/ |
| D | assembler-x64.cc | 98 if (cpu.has_sse3()) SetSupported(SSE3); in ProbeImpl()
121 if (!FLAG_enable_sse3) SetUnsupported(SSE3); in ProbeImpl()
122 if (!FLAG_enable_ssse3 || !IsSupported(SSE3)) SetUnsupported(SSSE3); in ProbeImpl()
149 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSSE3), in PrintFeatures()
363 EnableCpuFeature(SSE3); in Assembler()
2468 DCHECK(IsEnabled(SSE3)); in fisttp_s()
2476 DCHECK(IsEnabled(SSE3)); in fisttp_d()
3356 DCHECK(IsEnabled(SSE3)); in haddps()
3366 DCHECK(IsEnabled(SSE3)); in haddps()
4299 DCHECK(IsEnabled(SSE3)); in lddqu()
[all …]
|
| /third_party/node/deps/v8/src/codegen/shared-ia32-x64/ |
| D | macro-assembler-shared-ia32-x64.cc | 845 CpuFeatureScope sse_scope(this, SSE3); in I64x2Abs()
875 CpuFeatureScope sse_scope(this, SSE3); in I64x2GtS()
908 CpuFeatureScope sse_scope(this, SSE3); in I64x2GeS()
|
| D | macro-assembler-shared-ia32-x64.h | 191 AvxHelper<Dst, Arg, Args...>{this, base::Optional<CpuFeature>(SSE3)} \
|
| /third_party/openssl/doc/man3/ |
| D | OPENSSL_ia32cap.pod | 45 =item bit #41 denoting SSSE3, Supplemental SSE3, support;
|
| /third_party/mesa3d/docs/drivers/ |
| D | llvmpipe.rst | 18 SSE2 is strongly encouraged. Support for SSE3 and SSE4.1 will yield
|
| /third_party/node/deps/v8/src/builtins/ia32/ |
| D | builtins-ia32.cc | 3158 if (CpuFeatures::IsSupported(SSE3)) { in Generate_DoubleToI()
3159 CpuFeatureScope scope(masm, SSE3); in Generate_DoubleToI()
3174 if (CpuFeatures::IsSupported(SSE3)) { in Generate_DoubleToI()
3185 if (CpuFeatures::IsSupported(SSE3)) { in Generate_DoubleToI()
3186 CpuFeatureScope scope(masm, SSE3); in Generate_DoubleToI()
|
| /third_party/node/deps/v8/infra/testing/ |
| D | builders.pyl | 176 # No SSE3.
|
| /third_party/ffmpeg/ |
| D | configure | 438 --disable-sse3 disable SSE3 optimizations
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IntrinsicsX86.td | 502 // SSE3
|
| /third_party/mesa3d/docs/relnotes/ |
| D | 7.10.rst | 1836 - llvmpipe: Fix MSVC build. Enable the new SSE2 code on non SSE3
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 269 …{ "sse3", "Enable SSE3 instructions", X86::FeatureSSE3, { { { 0x0ULL, 0x800000ULL, 0x0ULL, } } } },
23187 if (Bits[X86::FeatureSSE3] && X86SSELevel < SSE3) X86SSELevel = SSE3;
|