| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 196 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionBodyStart() local
198 if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) && in EmitFunctionBodyStart()
206 if (STM.isAmdHsaOS()) in EmitFunctionBodyStart()
258 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionEntryLabel() local
259 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) { in EmitFunctionEntryLabel()
430 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
433 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) { in runOnMachineFunction()
449 if (STM.isAmdPalOS()) in runOnMachineFunction()
451 else if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
456 if (STM.dumpCode()) { in runOnMachineFunction()
[all …]
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| D | SILoadStoreOptimizer.cpp | 182 const GCNSubtarget &STM);
201 const GCNSubtarget *STM = nullptr; member in __anon885512d60111::SILoadStoreOptimizer
214 static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI,
469 const GCNSubtarget &STM) { in setMI() argument
489 EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4); in setMI()
809 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, in widthsFit() argument
815 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3)); in widthsFit()
910 Paired.setMI(MBBI, *TII, *STM); in findMatchingInst()
917 : widthsFit(*STM, CI, Paired) && offsetsCanBeCombined(CI, *STI, Paired); in findMatchingInst()
939 if (STM->ldsRequiresM0Init()) in read2Opcode()
[all …]
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| D | R600AsmPrinter.cpp | 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
48 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
71 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { in EmitProgramInfoR600()
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| D | AMDGPUHSAMetadataStreamer.cpp | 213 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSACodeProps() local
222 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, in getHSACodeProps()
228 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
233 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); in getHSACodeProps()
891 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSAKernelProps() local
899 STM.getKernArgSegmentSize(F, MaxKernArgAlign)); in getHSAKernelProps()
907 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
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| D | SIMemoryLegalizer.cpp | 860 const GCNSubtarget &STM = MBB.getParent()->getSubtarget<GCNSubtarget>(); in insertCacheInvalidate() local
862 const unsigned Flush = STM.isAmdPalOS() || STM.isMesa3DOS() in insertCacheInvalidate()
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| /third_party/openssl/test/recipes/30-test_evp_data/ |
| D | evpmd_sha.txt | 158 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
266 # http://csrc.nist.gov/groups/STM/cavp/secure-hashing.html#test-vectors
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| /third_party/libphonenumber/resources/carrier/en/ |
| D | 977.txt | 16 977960|STM Telecom
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| /third_party/mesa3d/src/imagination/vulkan/pds/ |
| D | pvr_rogue_pds_disasm.h | 63 X(STM) \
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| /third_party/jerryscript/targets/mbedos5/ |
| D | README.md | 13 - [STM NUCLEO F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | DataLayout.cpp | 617 StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap); in getStructLayout() local
618 StructLayout *&SL = (*STM)[Ty]; in getStructLayout()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleM4.td | 62 def : M4UnitL1I<(instregex "(t|t2)STM")>;
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| D | ARMScheduleR52.td | 506 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
508 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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| D | ARMScheduleSwift.td | 535 (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
537 (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
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| D | ARMBaseInstrInfo.cpp | 1518 MachineInstrBuilder LDM, STM; in expandMEMCPY() local
1531 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD in expandMEMCPY()
1536 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA)); in expandMEMCPY()
1543 STM.add(STBase).add(predOps(ARMCC::AL)); in expandMEMCPY()
1558 STM.addReg(Reg, RegState::Kill); in expandMEMCPY()
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| D | ARMScheduleA57.td | 715 def : InstRW<[A57WriteSTM], (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$")>;
717 (instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH")>;
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| D | ARMInstrThumb.td | 830 // There is no non-writeback version of STM for Thumb.
1634 // post-inc STR -> STM r0!, {r1}. The layout of this (because it doesn't def
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| /third_party/node/deps/v8/src/execution/s390/ |
| D | simulator-s390.h | 590 EVALUATE(STM);
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| D | simulator-s390.cc | 919 EvalTable[STM] = &Simulator::Evaluate_STM; in EvalTableInit()
5810 EVALUATE(STM) { in EVALUATE() argument
5811 DCHECK_OPCODE(STM); in EVALUATE()
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| /third_party/node/deps/v8/src/codegen/s390/ |
| D | constants-s390.h | 1032 V(stm, STM, 0x90) /* type = RS_A STORE MULTIPLE (32) */ \
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 256 def : InstRW<[WLat1, LSU2, FXU5, GroupAlone], (instregex "STM(H|Y|G)?$")>;
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| D | SystemZScheduleZEC12.td | 267 def : InstRW<[WLat1, LSU2, FXU5, GroupAlone], (instregex "STM(H|Y|G)?$")>;
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| D | SystemZScheduleZ13.td | 293 def : InstRW<[WLat1, LSU2, FXb3, GroupAlone], (instregex "STM(G|H|Y)?$")>;
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| D | SystemZScheduleZ14.td | 294 def : InstRW<[WLat1, LSU2, FXb3, GroupAlone], (instregex "STM(G|H|Y)?$")>;
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| /third_party/node/deps/openssl/openssl/providers/fips/ |
| D | self_test_data.inc | 615 * https://csrc.nist.rip/groups/STM/cavp/documents/drbg/drbgtestvectors.zip
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| /third_party/openssl/providers/fips/ |
| D | self_test_data.inc | 615 * https://csrc.nist.rip/groups/STM/cavp/documents/drbg/drbgtestvectors.zip
|