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Searched refs:ShiftVal (Results 1 – 21 of 21) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
268 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
288 ShiftVal = 12; in getAddSubImmOpValue()
290 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
528 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
529 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
534 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
555 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
556 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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DAArch64InstPrinter.cpp995 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1007 if (ShiftVal != 0) in printArithExtend()
1008 O << ", lsl #" << ShiftVal; in printArithExtend()
1013 if (ShiftVal != 0) in printArithExtend()
1014 O << " #" << ShiftVal; in printArithExtend()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Utils/
DRISCVMatInt.cpp84 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
85 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp75 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
76 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
DAArch64FastISel.cpp1262 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1268 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1286 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1293 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1648 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1655 RHSIsKill, ShiftVal); in emitLogicalOp()
1665 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1671 RHSIsKill, ShiftVal); in emitLogicalOp()
4702 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4731 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
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DAArch64ISelDAGToDAG.cpp418 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
419 if (ShiftVal > 3) in isWorthFoldingSHL()
687 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
694 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
695 if (ShiftVal > 4) in SelectArithExtendedRegister()
723 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
944 unsigned ShiftVal = CSD->getZExtValue(); in SelectExtendedSHL() local
946 if (ShiftVal != 0 && ShiftVal != LegalShiftVal) in SelectExtendedSHL()
DAArch64InstrInfo.cpp774 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
775 if (ShiftVal == 0) in isFalkorShiftExtFast()
777 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
801 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
802 return ShiftVal == 0 || in isFalkorShiftExtFast()
803 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
809 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
810 return ShiftVal == 0 || in isFalkorShiftExtFast()
811 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
DAArch64InstructionSelector.cpp4708 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
4711 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
4795 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
4812 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
4813 if (ShiftVal > 4) in selectArithExtendedRegister()
4849 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMParallelDSP.cpp790 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
791 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp1539 SDValue ShiftVal = Op.getOperand(1); in unrollVectorShift() local
1543 DL, ShiftVal.getValueType(), // masked value type in unrollVectorShift()
1544 ShiftVal, // original shift value operand in unrollVectorShift()
1545 DAG.getConstant(MaskVal, DL, ShiftVal.getValueType()) // mask operand in unrollVectorShift()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2266 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2275 ShiftVal = Amount; in isSimpleShift()
2424 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2427 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2428 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2429 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2431 MaskVal >> ShiftVal, in adjustForTestUnderMask()
2432 CmpVal >> ShiftVal, in adjustForTestUnderMask()
2435 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2438 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp1964 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1971 Srl.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
1986 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
1987 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
1993 And.getOperand(0), ShiftVal, WidthVal)); in SelectS_BFE()
DAMDGPUISelLowering.cpp4076 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32); in PerformDAGCombine() local
4078 BitsFrom, ShiftVal); in PerformDAGCombine()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineCasts.cpp464 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
467 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
474 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
DInstCombineCompares.cpp2026 const APInt *ShiftVal; in foldICmpShlConstant() local
2027 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2028 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
2174 const APInt *ShiftVal; in foldICmpShrConstant() local
2175 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal))) in foldICmpShrConstant()
2176 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal); in foldICmpShrConstant()
DInstCombineCalls.cpp501 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
502 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
508 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DAutoUpgrade.cpp1011 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in UpgradeX86ALIGNIntrinsics() local
1020 ShiftVal &= (NumElts - 1); in UpgradeX86ALIGNIntrinsics()
1024 if (ShiftVal >= 32) in UpgradeX86ALIGNIntrinsics()
1029 if (ShiftVal > 16) { in UpgradeX86ALIGNIntrinsics()
1030 ShiftVal -= 16; in UpgradeX86ALIGNIntrinsics()
1039 unsigned Idx = ShiftVal + i; in UpgradeX86ALIGNIntrinsics()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp1993 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2009 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp3027 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
3028 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
DX86ISelLowering.cpp7417 uint64_t ShiftVal = N.getConstantOperandVal(1); in getFauxShuffleMask() local
7419 if (NumBitsPerElt <= ShiftVal) { in getFauxShuffleMask()
7425 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
7428 uint64_t ByteShift = ShiftVal / 8; in getFauxShuffleMask()
7933 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); in getVShift() local
7934 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
17720 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT() local
17721 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
17723 DAG.getConstant(ShiftVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT()
17731 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
DValueTracking.cpp2252 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1); in isKnownNonZero() local
2254 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal) in isKnownNonZero()
2257 if (Known.countMinTrailingZeros() >= ShiftVal) in isKnownNonZero()