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Searched refs:SpillSize (Results 1 – 7 of 7) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h233 unsigned RegSize, SpillSize, SpillAlignment; member
278 return getRegClassInfo(RC).SpillSize / 8; in getSpillSize()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DStatepointLowering.cpp98 unsigned SpillSize = ValueType.getStoreSize(); in allocateStackSlot() local
99 assert((SpillSize * 8) == ValueType.getSizeInBits() && "Size not in bytes?"); in allocateStackSlot()
115 if (MFI.getObjectSize(FI) == SpillSize) { in allocateStackSlot()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp512 unsigned SpillSize; in foldPatchpoint() local
518 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
522 MIB.addImm(SpillSize); in foldPatchpoint()
DLiveDebugVariables.cpp1202 unsigned SpillSize; in rewriteLocations() local
1205 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1068 unsigned SpillSize = TRI->getSpillSize(*RC); in storeRegToStackSlot() local
1076 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize)); in storeRegToStackSlot()
1080 if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) { in storeRegToStackSlot()
1099 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1100 : getVGPRSpillSaveOpcode(SpillSize); in storeRegToStackSlot()
1191 unsigned SpillSize = TRI->getSpillSize(*RC); in loadRegFromStackSlot() local
1205 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize)); in loadRegFromStackSlot()
1206 if (Register::isVirtualRegister(DestReg) && SpillSize == 4) { in loadRegFromStackSlot()
1221 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
1222 : getVGPRSpillRestoreOpcode(SpillSize); in loadRegFromStackSlot()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp5410 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode() local
5411 assert((SpillSize == 64 || STI.hasVLX()) && in getBroadcastOpcode()
5417 switch (SpillSize) { in getBroadcastOpcode()
5425 switch (SpillSize) { in getBroadcastOpcode()
5433 switch (SpillSize) { in getBroadcastOpcode()
5441 switch (SpillSize) { in getBroadcastOpcode()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td62 int SpillSize = SS; // Spill slot size in bits.