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Searched refs:Src1RC (Results 1 – 5 of 5) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1593 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1595 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1600 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1626 Src1Mod:$src1_modifiers, Src1RC:$src1,
1629 Src1Mod:$src1_modifiers, Src1RC:$src1,
1634 (ins Src0RC:$src0, Src1RC:$src1, clampmod0:$clamp),
1635 (ins Src0RC:$src0, Src1RC:$src1))
1644 Src1Mod:$src1_modifiers, Src1RC:$src1,
1649 Src1Mod:$src1_modifiers, Src1RC:$src1,
1653 Src1Mod:$src1_modifiers, Src1RC:$src1,
[all …]
DSIFixSGPRCopies.cpp676 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
679 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
682 TRI->hasVectorRegisters(Src1RC))) { in runOnMachineFunction()
DVOP1Instructions.td272 class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
277 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
278 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
DSIInstrInfo.cpp5372 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalar64BitAddSub() local
5374 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
5378 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
5384 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
5440 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
5444 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
5448 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
5452 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
DAMDGPUInstructionSelector.cpp614 const TargetRegisterClass *Src1RC = in selectG_INSERT() local
625 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()