| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
324 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
326 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup()
328 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) { in getDuplexCandidateGroup()
332 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
340 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
342 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
359 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
361 if (HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getDuplexCandidateGroup()
369 Src1Reg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
[all …]
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| D | HexagonMCCompound.cpp | 80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
97 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
100 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
142 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
144 HexagonMCInstrInfo::isIntRegForSubInst(Src1Reg) && in getCompoundCandidateGroup()
156 Src1Reg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
157 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg) in getCompoundCandidateGroup()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPostRewrite.cpp | 111 Register Src1Reg = MBBI->getOperand(1).getReg(); in selectSELRMux() local
114 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
139 if (DestReg != Src1Reg && DestReg == Src2Reg) { in selectSELRMux()
141 std::swap(Src1Reg, Src2Reg); in selectSELRMux()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1177 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1179 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1180 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1201 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1204 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1205 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3309 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
3313 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg)) in getCompoundCandidateGroup()
3346 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 275 Register Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 415 Register Src1Reg = I.getOperand(3).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
436 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_UADDO_USUBO_UADDE_USUBE()
590 Register Src1Reg = I.getOperand(2).getReg(); in selectG_INSERT() local
591 LLT Src1Ty = MRI->getType(Src1Reg); in selectG_INSERT()
611 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
625 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
631 .addReg(Src1Reg) in selectG_INSERT()
653 Register Src1Reg = I.getOperand(3).getReg(); in selectG_INTRINSIC() local
657 for (Register Reg : { DstReg, Src0Reg, Src1Reg }) in selectG_INTRINSIC()
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| D | R600InstrInfo.cpp | 1242 unsigned Src1Reg) const { in buildDefaultInstruction()
1246 if (Src1Reg) { in buildDefaultInstruction()
1260 if (Src1Reg) { in buildDefaultInstruction()
1261 MIB.addReg(Src1Reg) // $src1 in buildDefaultInstruction()
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| D | R600InstrInfo.h | 271 unsigned Src1Reg = 0) const;
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| D | AMDGPURegisterBankInfo.cpp | 2995 Register Src1Reg = MI.getOperand(3).getReg(); in getInstrMapping() local
2997 unsigned Src1Size = MRI.getType(Src1Reg).getSizeInBits(); in getInstrMapping()
3002 OpdsMapping[3] = AMDGPU::getValueMapping(getRegBankID(Src1Reg, MRI, *TRI), in getInstrMapping()
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| D | SIInstrInfo.cpp | 2408 Register Src1Reg = Src1->getReg(); in FoldImmediate() local
2410 Src0->setReg(Src1Reg); in FoldImmediate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1047 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
1051 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1069 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg); in selectSelect()
1942 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
1943 if (!Src0Reg || !Src1Reg) in selectDivRem()
1946 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2689 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2690 if (!Src1Reg) in optimizeSelect()
2700 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1); in optimizeSelect()
2703 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2819 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
2825 if (!Src1Reg || !Src2Reg) in selectSelect()
2829 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2833 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
4666 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4667 if (!Src1Reg) in selectRem()
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| D | AArch64InstructionSelector.cpp | 1102 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorSHL() local
1125 auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg}); in selectVectorSHL()
1140 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorASHR() local
1173 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg}); in selectVectorASHR()
2822 Register Src1Reg = I.getOperand(1).getReg(); in selectMergeValues() local
2826 emitLaneInsert(None, Tmp.getReg(0), Src1Reg, /* LaneIdx */ 0, RB, MIB); in selectMergeValues()
3777 Register Src1Reg = I.getOperand(1).getReg(); in selectShuffleVector() local
3778 const LLT Src1Ty = MRI.getType(Src1Reg); in selectShuffleVector()
3821 MachineInstr *Concat = emitVectorConcat(None, Src1Reg, Src2Reg, MIRBuilder); in selectShuffleVector()
3850 {&AArch64::QQRegClass}, {Src1Reg}) in selectShuffleVector()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4200 Register Src1Reg = MI.getOperand(2).getReg(); in lowerShuffleVector() local
4217 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; in lowerShuffleVector()
4236 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); in lowerShuffleVector()
4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector()
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