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Searched refs:SrcIdx (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp156 unsigned SrcIdx, unsigned DstIdx,
1271 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1278 Register regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1287 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1313 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1467 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1469 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1472 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1494 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
[all …]
DRegisterCoalescer.h40 unsigned SrcIdx = 0; variable
104 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DRegisterCoalescer.cpp428 SrcIdx = DstIdx = 0; in setRegisters()
475 SrcIdx, DstIdx); in setRegisters()
480 SrcIdx = DstSub; in setRegisters()
497 if (DstIdx && !SrcIdx) { in setRegisters()
499 std::swap(SrcIdx, DstIdx); in setRegisters()
518 std::swap(SrcIdx, DstIdx); in flip()
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
556 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1238 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1281 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
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DPeepholeOptimizer.cpp1845 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1855 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1858 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1863 if (SrcIdx >= Def->getNumOperands()) in getNextSourceFromBitcast()
1873 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
DTargetRegisterInfo.cpp352 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
355 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp2275 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2284 SrcIdx = 1; MaskIdx = 5; break; in EmitInstruction()
2288 SrcIdx = 2; MaskIdx = 6; break; in EmitInstruction()
2292 SrcIdx = 3; MaskIdx = 7; break; in EmitInstruction()
2304 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask)); in EmitInstruction()
2333 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
2342 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; in EmitInstruction()
2346 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; in EmitInstruction()
2350 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; in EmitInstruction()
2356 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; in EmitInstruction()
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DX86ISelLowering.cpp7038 unsigned SrcIdx = M / Size; in getTargetShuffleAndZeroables() local
7064 if (IsSrcConstant[SrcIdx]) { in getTargetShuffleAndZeroables()
7065 if (UndefSrcElts[SrcIdx][M]) in getTargetShuffleAndZeroables()
7067 else if (SrcEltBits[SrcIdx][M] == 0) in getTargetShuffleAndZeroables()
7330 unsigned SrcIdx = SrcExtract.getConstantOperandVal(1); in getFauxShuffleMask() local
7331 if (NumSrcElts <= SrcIdx) in getFauxShuffleMask()
7335 Mask.push_back(SrcIdx); in getFauxShuffleMask()
7653 uint64_t SrcIdx = N->getConstantOperandVal(1); in getShuffleScalarElt() local
7654 return getShuffleScalarElt(Src.getNode(), Index + SrcIdx, DAG, Depth + 1); in getShuffleScalarElt()
12173 int SrcIdx = i + Offset; in lowerShuffleAsSpecificZeroOrAnyExtend() local
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DX86InstrInfo.cpp1633 unsigned SrcIdx = (Imm >> 6) & 3; in commuteInstructionImpl() local
1637 if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 && in commuteInstructionImpl()
4741 unsigned SrcIdx = (Imm >> 6) & 3; in foldMemoryOperandCustom() local
4747 int PtrOffset = SrcIdx * 4; in foldMemoryOperandCustom()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp254 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
270 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
315 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
316 if (SrcIdx < 0) in getSrcs()
318 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1400 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1422 switch (SrcIdx) { in getFlagOp()
1439 switch (SrcIdx) { in getFlagOp()
DR600InstrInfo.h112 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
310 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600ISelLowering.h101 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
DR600ISelLowering.cpp2069 bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx, in FoldOperand() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DInferAddressSpaces.cpp961 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local
962 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces()
968 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
976 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2913 for (int SrcIdx : SrcIndices) { in validateEarlyClobberLimitations() local
2914 if (SrcIdx == -1) break; in validateEarlyClobberLimitations()
2915 const MCOperand &Src = Inst.getOperand(SrcIdx); in validateEarlyClobberLimitations()
3270 for (int SrcIdx : SrcIndices) { in validateLdsDirect() local
3271 if (SrcIdx == -1) break; in validateLdsDirect()
3272 const MCOperand &Src = Inst.getOperand(SrcIdx); in validateLdsDirect()
4833 int SrcIdx = 0; in cvtExp() local
4840 assert(SrcIdx < 4); in cvtExp()
4841 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
4843 ++SrcIdx; in cvtExp()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp1030 for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) { in simplifyAMDGCNMemoryIntrinsicDemanded() local
1031 const unsigned Bit = 1 << SrcIdx; in simplifyAMDGCNMemoryIntrinsicDemanded()
DInstCombineVectorOps.cpp411 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); in visitExtractElementInst() local
416 if (SrcIdx < 0) in visitExtractElementInst()
418 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
421 SrcIdx -= LHSWidth; in visitExtractElementInst()
427 SrcIdx, false)); in visitExtractElementInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp419 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg() argument
423 SrcIdx.push_back(-1); in buildHvxVectorReg()
438 SrcIdx.push_back(I); in buildHvxVectorReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
DSimplifyCFG.cpp4063 for (unsigned SrcIdx = 0, SrcE = SrcPN->getNumIncomingValues(); in removeEmptyCleanup() local
4064 SrcIdx != SrcE; ++SrcIdx) { in removeEmptyCleanup()
4065 DestPN->addIncoming(SrcPN->getIncomingValue(SrcIdx), in removeEmptyCleanup()
4066 SrcPN->getIncomingBlock(SrcIdx)); in removeEmptyCleanup()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2871 int SrcIdx = NarrowNumElts * I + J; in fewerElementsVectorBuildVector() local
2873 if (SrcIdx < DstNumElts) { in fewerElementsVectorBuildVector()
2874 Register SrcReg = MI.getOperand(SrcIdx + 1).getReg(); in fewerElementsVectorBuildVector()